EDK Overview

1. EDK Overview Dr.K

2. Embedded Development Kit • What is Embedded Development Kit (EDK)? • The Embedded Development Kit is the Xilinx software suite for designing complete embedded programmable systems • The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC™ hard processor cores, and/or Xilinx MicroBlaze™ soft processor cores • It enables the integration of both hardware and software components of an embedded system

3. Where to get EDK? • $495 to buy(from www.avnet.com, www.nuhorizons.com) • 30-day evaluation is available (www.xilinx.com/ise_eval/index.htm) • EDK Manuals & Application Notes(www.xilinx.com/ise/embedded/edk_pstudio.htm)

4. Current Technologiesfor Embedded Systems • Microcontroller-based systems • DSP processor-based systems • ASIC technology • FPGA technology

5. Embedded Design in an FPGA • Embedded design in an FPGA consists of the following: • Develop FPGA hardware design • Generate drivers and libraries • Create the software application • Software routines • Interrupt service routines (optional) • Operating System (OS) or Real Time Operating System (RTOS) (optional)

6. Bus Bridge Arbiter Arbiter On-Chip Peripheral Bus Processor Local Bus MicroBlaze Processor-Based Embedded Design I-Cache BRAM Flexible Soft IP Local Memory Bus MicroBlaze 32-Bit RISC Core BRAM Configurable Sizes D-Cache BRAM Fast Simplex Link PLB OPB 0,1….15 Custom Functions Custom Functions On-Chip Peripheral Memory Controller 10/100 E-Net UART GPIO CacheLink Off-Chip Memory FLASH/SRAM SDRAM This is a v7.1 architecture. Versions 6.0 or earlier do not support PLB bus off the processor. Instead they have OPB bus

7. Microblaze Processor • MicroBlaze is a 32-bit RISC processor modeled on DLXi (see Henessy and Patterson's book). • Soft-configurable (many options like cache, FPU) • Contains 32 general purpose registers (R0…R31) • Single-issue 3-5 stage pipelined processor which operates on 32-bit instructions with 3 operands and 2 addressing modes. ; Load the value 0x70000000 ; into register r5 XOR r5, r5, r5 ORI r5, r5, 0x7000000

8. IP Cores See IP Catalog or Xilinx web for Complete Listing of free and evaluation IP Cores • Open-source cores are available at www.opencores.org • Xilinx has created a wide variety of IP cores: • Bus infrastructure cores • Busses: PLB, OPB • Bridges: PLB2OPB , OPB2PLB • Communication: High-Speed • 10/100 Ethernet MAC, CAN controller, HDLC Interface, Flexray, MOST, USB2 • Communication: Low-Speed • Serial Peripheral Interface, IIC Interface, UART 16550, UART lite • DMA and Counter • Fixed interval timer, watchdog timer, central DMA controller • Memory Controllers for • Block RAM, DDR/DDR2/SDRAM (multi-port available), SRAM/Flash (multi-port available), Compact Flash • General Purpose I/O • General Purpose I/O (GPIO) • Interprocessor Communication • Mailbox, MUTEX

9. Memory Mapped I/O • A single set of instructions used to access memory and all peripherals. • Memory access latency is 5 clock cycles (typical). • Peripheral access latency is 50 clock cycles (empty bus).

10. Bus Bridge Arbiter Arbiter On-Chip Peripheral Bus Processor Local Bus What is unique about FPGA EDK? ANSWER: Fast Simplex Links I-Cache BRAM Local Memory Bus MicroBlaze 32-Bit RISC Core BRAM Configurable Sizes D-Cache BRAM Fast Simplex Link PLB OPB 0,1….15 Custom Functions Custom Functions On-Chip Peripheral Memory Controller 10/100 E-Net UART GPIO CacheLink Off-Chip Memory FLASH/SRAM SDRAM

11. FIFO 32-bit data Fast Simplex Links ( FSL) • Unidirectional point-to-point FIFO-based communication • Dedicated (unshared) and nonarbitrated architecture • Dedicated MicroBlaze™ C and ASM instructions for easy access • High speed, access in as little as two clocks on processor side, 600 MHz at hardware interface • Available in Xilinx Platform Studio (XPS) as a bus interface library core from Hardware → Create or Import Peripheral Wizard FSL_M_Clk FSL_S_Clk FSL_M_Data [0:31] FSL_S_Data [0:31] FSL_M_Control FSL_S_Control FSL_M_Write FSL_S_Read FSL_M_Full FSL_S_Exists FIFO Depth

12. VHDL or Verilog C Code Standard Embedded SW Development Flow Standard FPGA HW Development Flow Embedded Development Kit Code Entry HDL Entry C/C++ Cross Compiler Simulation/Synthesis Board Support Package System Netlist Data2MEM Linker Implementation Compiled ELF Compiled ELF Compiled BIT Compiled BIT ? ? Download Combined Image to FPGA Load Software Into FLASH Download Bitstream Into FPGA Debugger Chipscope Embedded DevelopmentTool Flow Overview Instantiate the ‘System Netlist’ and Implement the FPGA Include the BSP and Compile the Software Image 2 3 1 RTOS, Board Support Package

13. Embedded Design Flow • Develop the embedded hardware • Quickly create a system targeting a board using Base System Builder Wizard • Extend the hardware system • Add peripherals from the IP Catalog • Create and add a custom peripheral using the Create/Import Peripherals Wizard • Insert ChipScope™ Pro cores into the system using the Debug Configuration Wizard • Generate HDL netlists using PlatGen • Perform an HDL simulation using an HDL simulator • Generate simulation models using SimGen • Develop the embedded software • Generate libraries and drivers with LibGen • Create and debug the software ap in XPS or the Software Development Kit (SDK) • Compile using the GNU C/C++ compiler (gcc) • Connect to the target using Xilinx Microprocessor Debug (XMD) • Debug using the GNU debugger (gdb) • Operate in hardware • Generate the bitstream and configure the FPGA • The bitstream initializer (BitInit) will update FPGA instruction memory with the executable • Initialize external flash memory • Write to external flash using the Flash Writer utility • Generate an external compact flash configuration file using the System ACE File generator (GenACE)

14. Demo Time • Start a New Project • Select Microprocessor • Select Peripherals • Setup Software • Download bit file to FPGA • Finish up!