introducci n al edk l.
Skip this Video
Loading SlideShow in 5 Seconds..
Introducción al EDK PowerPoint Presentation
Download Presentation
Introducción al EDK

Loading in 2 Seconds...

play fullscreen
1 / 33

Introducción al EDK - PowerPoint PPT Presentation

Download Presentation
Introducción al EDK
An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Introducción al EDK

  2. Embedded DevelopmentTool Flow Overview VHDL or Verilog C Code Standard Embedded SW Development Flow Standard FPGA HW Development Flow Embedded Development Kit Code Entry HDL Entry C/C++ Cross Compiler Simulation/Synthesis Board Support Package System Netlist Data2MEM Linker Implementation Compiled ELF Compiled ELF Compiled BIT Compiled BIT ? ? Download Combined Image to FPGA Load Software Into FLASH Download Bitstream Into FPGA Debugger Chipscope Instantiate the ‘System Netlist’ and Implement the FPGA Include the BSP and Compile the Software Image 2 3 1 RTOS, Board Support Package

  3. Embedded DevelopmentTool Flow Overview • While seemingly complex when viewed in total, the system design flow simply combines the standard hardware flow used to create FPGA bitstreams and standard software flow used to create processor ELF files. In fact, unless on-chip memory resources are used to store the software image, the Embedded Developers Kit can be viewed as nothing more than an extension to the Xilinx core generation tool CoreGen. • The first step is to create the ‘System Netlist’ using the Embedded Developers Kit and instantiate that netlist into the design’s HDL code. The hardware design is then synthesized, merged and implemented using the exact same flow as used with any other ‘black box’ core. While it is common to include a portion of the yet created software image inside the FPGA using block RAM, the ‘Compiled BIT’ file created during this phase of development only contains the systems hardware description.

  4. Embedded DevelopmentTool Flow Overview • The second step is to create the ‘Board Support Package’ (BSP) using the Embedded Developers Kit (EDK) and include the required drivers in the system’s C code. The code is then compiled and linked with the various functions available in the BSP as is the same with any other processor system. Because the embedded system is built using the FPGA fabric, the BSP is customized for the particular set of peripherals included in the ‘System Netlist’. Unlike an off the shelf general purpose processor, embedded systems in Xilinx FPGA can include any combination of Xilinx provided and user created peripherals. This means that every BSP is potentially unique and as such EDK is tasked with customizing a generic set of drivers as required to properly support the ‘arbitrary processor system’. • Once the final set of peripherals and bus structures have been solidified, the software and hardware flows can be run independently. Even if part or all of the software image is stored using on-chip block RAM, the software flow does not require running the hardware flow from scratch when making software changes. Only if a change is made to the instantiated ‘System Netlist’ does the hardware need to be implemented again before a the new software image which relies on the architectural change can be loaded and run.

  5. Embedded DevelopmentTool Flow Overview • If the software image is completely stored externally, configuring the FPGA and loading the external storage device are performed in exactly the same way as a typical two chip solution. If part or all of the software image is stored using on-chip block RAM and as such is embedded within the FPGA’s bitstream, an additional step is required before the FPGA can be configured. EDK provides a tool called Data2MEM which merges the appropriate sections of the ‘Compiled ELF’ file with the ‘Compiled BIT’ file. The resulting BIT file is created is typically created in a few seconds and can then be used to configured the FPGA. When the entire software image is stored within the FPGA, only the BIT file is needed to both configure the system and load the software image. If only portion of the software image, such as the bootstrap, is stored within the FPGA, then Data2MEM is run to create a combined BIT file and the system is once again configured/loaded as any two chip solution using the unmerged ELF sections and the combined BIT file.

  6. Embedded DevelopmentTool Flow Overview • Debugging the software running on the system is performed in the same manner as would be on any general purpose processor. GDB or other debug tool is used to connect to the target and provide runtime control of the target and even load new images when desired. Unlike general purpose processors, the physical system can be probed using ChipScope modules. This capability provides a level of visibility into the operation of the system unmatched by external processors.

  7. EDK tools • Xilinx® EDK comprises the following tools: • Xilinx Platform Studio (XPS) • XPS provides an integrated environment for creating software and hardware specification flows for embedded processor systems based on MicroBlaze™ and PowerPC® processors. • XPS offers customization of tool flow configuration options and provides a graphical system editor for connection of processors, peripherals, and buses. •  Hardware Platform Generation Tool • The Hardware Platform Generation tool (Platgen) customizes and generates the embedded processor system, in the form of hardware netlists (Hardware Description Language (HDL) files). • By default, Platgen synthesizes each processor IP core instance found in your embedded hardware design using the XST compiler. Platgen also generates the system-level HDL file that interconnects all the IP cores, to be synthesized later as part of the overall Xilinx® ISE® implementation flow.

  8. EDK tools • Base System Builder Wizard • The Base System Builder (BSB) wizard allows you to quickly create a working embedded design, using any features of a supported development board or using basic functionality common to most embedded systems. After you create a basic system, you can then customize it using the tools in XPS and ISE. Xilinx recommends using the BSB. •  Simulation Model Generation Tool • The Simulation Model Generation tool (Simgen) generates simulation models of your embedded hardware system based either on your original embedded hardware design (behavioral) or finished FPGA implementation (timing-accurate). Simgen can also incorporate your embedded software to run on the model. • Create and Import Peripheral Wizard • The Create and Import Peripheral wizard helps you create your own peripherals and import them into EDK-compliant repositories or XPS projects. The wizard can create an HDL template for your custom logic and provides an interface to one of the supported IBM CoreConnect or Xilinx FSL buses.

  9. EDK tools • Software Development Kit • The Xilinx Software Development Kit (SDK) is the recommended development environment for software application projects. SDK is based on the Eclipse open source standard. • Note XPS can also be used for software development. However, all software development tools available in XPS is deprecated and will be removed in the 12.1 release. • Library Generation Tool • The Library Generation tool (Libgen) configures libraries, device drivers, file systems, and interrupt handlers for the embedded processor system, creating a software platform. • Version Management Tools • The Format Revision Tool updates design files to the current format. The Version Management wizard helps migrate IPs and drivers created with an earlier EDK release to the latest version.

  10. EDK tools •  Bitstream Initializer • The Bitstream Initializer (Bitinit) updates an FPGA configuration bitstream to initialize the on-chip instruction memory with the software executable.   •  Flash Memory Programming • Allows you to use your target processor to program on-board Common Flash Interface (CFI)-compliant parallel flash devices with software and data. •  GNU Software Development Tools • Embedded software applications written in C, C++, or Assembler are compiled using the GNU compiler tool chain. The GNU tool chain is part of the EDK and customized to target the PowerPC and MicroBlaze processors. •  Xilinx Microprocessor Debugger and GNU Software Debugging Tools • Using Xilinx Microprocessor Debugger (XMD) and GNU Debugger (GDB), you can debug your embedded application either on the host development system using an instruction set simulator, or on a board that has a Xilinx FPGA loaded with your hardware bitstream.

  11. EDK tools •   System ACE™ File Generation • The System ACE file generation tool (GenACE) generates a Xilinx System ACE™ configuration file based on the FPGA configuration bitstream and software executable to be stored in a non-volatile device in a production system. •  Xilinx Bash Shell • A Cygwin-based UNIX emulation shell that allows you to run command-line tools provided in the XPS and GNU tool chains.

  12. MicroBlaze based embedded systems • Compuesto por: • MicroBlaze soft processor core: • On-chip block RAM • Standard bus interconnects • On-chip Peripheral Bus (OPB) peripherals. • A MicroBlaze system can range from a processor core with a minimum of local memory to a large system with many MicroBlaze processors, sizable external memory, and numerous OPB peripherals. • MicroBlaze applications can range from software-based simple state machines to complex controllers for Internet appliances or other embedded applications.

  13. MicroBlaze based embedded systems • MicroBlaze soft processor core: • Orthogonal instruction set • 32 general purpose registers • Separate instruction and data buses (Harvard architecture) • Built-in interfaces to fast on-chip memory and to IBM’s industry-standard On-chip • Peripheral Bus (OPB) • On-chip block RAM • Standard bus interconnects • On-chip Peripheral Bus (OPB) peripherals.

  14. MicroBlaze based embedded systems • MicroBlaze soft processor core: • On-chip block RAM • Standard bus interconnects • The data side and instruction side bus interfaces each have an interface to local memory (called the Local Memory Bus, or LMB) and an interface to IBM’s On-chip Peripheral Bus (OPB). • LMB: single master bus protocol, apto para acceso rápido a Memoria en chip. (un ciclo) • OPB: 32 bits wide multi master bus protocol, apto para acceso a Periféricos y memoria externa. • On-chip Peripheral Bus (OPB) peripherals.

  15. MicroBlaze based embedded systems • MicroBlaze soft processor core • On-chip block RAM • Standard bus interconnects • On-chip Peripheral Bus (OPB) peripherals. • OPB peripherals complete the MicroBlaze hardware system and provide functions such as the following: • Watchdog timer • General purpose timer/counters • Interrupt controller • UARTs • General purpose I/O • Memory controllers. • In addition, you can define and add peripherals for custom functions, or as an interface to a design residing in the FPGA.

  16. MicroBlaze Architecture

  17. MicroBlaze Architecture • The MicroBlaze embedded soft core includes the following features: • Thirty-two 32-bit general purpose registers • 32-bit instruction word with three operands and two addressing modes • Separate 32-bit instruction and data buses that conform to IBM’s OPB (On-chip Peripheral Bus) specification • Separate 32-bit instruction and data buses with direct connection to on-chip block RAM through a LMB (Local Memory Bus) • 32-bit address bus • Single issue pipeline • Hardware multiplier (in Virtex-II and subsequent devices)

  18. Pipeline Architecture • The MicroBlaze pipeline is a parallel pipeline, divided into three stages: • Fetch • Decode • Execute • In general, each stage takes one clock cycle to complete. Consequently, it takes three clockcycles (ignoring any delays or stalls) for the instruction to complete.

  19. Load/Store Architecture • MicroBlaze can access memory in the following three data sizes: • Byte (8 bits) • Halfword (16 bits) • Word (32 bits) • Memory accesses are always data-size aligned. For halfword accesses, the least significant address bit is forced to 0. Similarly, for word accesses, the two least significant address bits are forced to 0. • MicroBlaze is a Big-Endian processor and uses the Big-Endian address and labeling conventions shown in Figure 2 when accessing memory. The following abbreviations are used: • MSByte: Most Significant Byte • LSByte: Least Significant Byte • MSBit: Most Significant Bit • LSBit: Least Significant Bit

  20. MicroBlaze Bus Interfaces • Arquitectura Harvard: buses independientes para instrucciones y datos • Cada Bus además, está replicado: • LMB: Local Memory Bus • OPB: On-Chip Peripherical Bus • Hay 6 configuraciones posibles del MicroBlaze:

  21. MicroBlaze Bus Interfaces

  22. Ejemplos

  23. Ejemplos. Configuración 1

  24. Ejemplos.

  25. Ejemplos: Configuración 3

  26. Ejemplos

  27. Ejemplos: Configuración 5

  28. Microprocessor Hardware Specification (MHS) format • In the initial phase of MicroBlaze platform design, you create an MHS (Microprocessor Hardware Specification) file that is used by the Platform Generator (PlatGen es una herramienta del SDK) . This file defines your platform configuration, and includes the following: • Peripherals • One of six configurations of the MicroBlaze bus interfaces • Connectivity of the system • Address space • Este archivo se crea automáticamente mediante las herramientas del EDK, pero es bueno conocer su sintaxis. Referenciar el manual de MicroBlaze.

  29. Microprocessor Peripheral Definition Format • The Platform Generator allows you to partition your peripherals into one or more reusable modules. The MPD file provides peripheral information to the Platform Generator, and has the following characteristics: • Lists ports and default connectivity for the OPB interface (as defined by IBM). Forexample, the MPD file can include information that maps a signal UART_xferAck to Sl_xferAck. • Can contain attributes set by you • Supplied by the IP provider • Any MPD option is overwritten by the equivalent MHS assignment (refer to theMicroprocessor Hardware Specification Format document for more details) • Individual peripheral documentation contains information on all MPD file options

  30. MicroBlaze Processor Scalable 32-bit Core Single-Issue pipeline Supports either 3-stage (resource focused) or 5-stage pipeline (performance focused) Configurable Instruction and Data Caches Direct mapped (1-way associative) Optional Memory Mgt or Memory Protection Unit Required for Linux OS (Linux 2.6 is currently supported) Floating-point unit (FPU) Based upon IEEE 754 format Barrel Shifter Hardware multiplier 32x32 multiplication to generate a 64-bit result Hardware Divider Fast Simplex Link FIFO Channels for Easy, Direct Access to Fabric and Hardware Acceleration Hardware Debug and Trace Module

  31. Busses 101 The MicroBlaze processor core is organized as a Harvard architecture IIC Multi-Port MemoryController UART CacheLinks GPIO IXCL DXCL Ethernet LocalMemory DPLB DLMB MicroBlaze™ BRAM ILMB IPLB FSL InterruptController Separate busses fordata and instruction Timer/PWM LMB Buses Co-Processor PLB ARB

  32. MicroBlaze System Bus Bridge Arbiter Arbiter On-Chip Peripheral Bus Processor Local Bus I-Cache BRAM Local Memory Bus MicroBlaze 32-Bit RISC Core BRAM Configurable Sizes D-Cache BRAM Fast Simplex Link PLB OPB 0,1….15 Custom Functions Custom Functions On-Chip Peripheral Memory Controller 10/100 E-Net UART GPIO CacheLink Off-Chip Memory FLASH/SRAM SDRAM