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Lecture 9 RTL Design Methodology Sorting Example

Lecture 9 RTL Design Methodology Sorting Example. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMD. S. Brown and Z. Vranesic , Fundamentals of Digital Logic with VHDL Design Chapter 10.2, Design Examples. Structure of a Typical Digital System. Data Inputs.

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Lecture 9 RTL Design Methodology Sorting Example

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  1. Lecture 9 RTL Design Methodology Sorting Example

  2. Required reading • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 6, FSMD • S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design • Chapter 10.2, Design Examples ECE 448 – FPGA and ASIC Design with VHDL

  3. Structure of a Typical Digital System Data Inputs Control & Status Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control & Status Outputs

  4. Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram State diagram or ASM chart Block diagram VHDL code VHDL code VHDL code

  5. Steps of the Design Process • Text description • Interface • Pseudocode • Block diagram of the Datapath • Interface with the division into the Datapath and the Controller • ASM chart of the Controller • RTL VHDL code of the Datapath, the Controller, and the Top Unit • Testbench of the Datapath, the Controller, and the Top Unit • Functional simulation and debugging • Synthesis and post-synthesis simulation • Implementation and timing simulation • Experimental testing

  6. Steps of the Design ProcessPracticed in Class Today • Text description • Interface • Pseudocode • Block diagram of the Datapath • Interface with the division into the Datapath and the Controller • ASM chart of the Controller • RTL VHDL code of the Datapath, the Controller, and the Top Unit • Testbench of the Datapath, the Controller, and the Top Unit • Functional simulation and debugging • Synthesis and post-synthesis simulation • Implementation and timing simulation • Experimental testing

  7. Sorting example

  8. Sorting Clock Resetn N N DataIn DataOut L RAdd Done WrInit S (0=initialization 1=computations) Rd Sorting - Required Interface

  9. Sorting - Required Interface

  10. Simulation results for the sort operation (1)Loading memory and starting sorting

  11. Simulation results for the sort operation (2)Completing sorting and reading out memory

  12. Sorting - Example During Sorting After sorting Before sorting i=0 i=0 i=0 i=1 i=1 i=2 j=1 j=2 j=3 j=2 j=3 j=3 Address 0 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3 1 1 1 1 2 2 3 4 Legend: position of memory indexed by i position of memory indexed by j Mj Mi

  13. Pseudocode FOR k = 4 FOR any k ≥ 2 [load input data] [load input data] - i = 0 2 i = 0 k 2 for to do for to do Mi Mi A = A = ; ; – j = i + 1 3 j = i + 1 k 1 for to do for to do B = Mj B = Mj ; ; B < A B < A if then if then Mi = B Mi = B ; ; Mj = A Mj = A ; ; A = Mi A = Mi ; ; endif ; endif ; endfor; endfor; endfor; endfor; [read output data] [read output data]

  14. Pseudocode wait for s=1 for i=0 to k-2 do A = Mi for j=i+1 to k-1 do B = Mj if A > B then Mi = B Mj = A A = Mi end if end for end for Done wait for s=0 go to the beginning

  15. EN RST CLK DataIn RAdd 0 ABMux N L L N LD Li Resetn 1 0 s EN RST Ei CLK Din Clock s +1 Csel WrInit DIN We LD Lj WE 0 Resetn L Addr EN RST i Ej Wr ADDR 0 CLK Clock CLK 1 Clock L L j DOUT 1 N Mij = k-1 EB EA = k-2 Resetn Resetn EN RST CLK Clock Clock Rd zi N zj N N Bout 0 1 B A DataOut A>B Block diagram of the Datapath AgtB

  16. Interface with the division into the Datapath and the Controller DataIn RAddr WrInit Clock Rd Resetn s N L AgtB zi zj Datapath Controller Wr Li Ei Lj Ej EA EB Bout Csel N DataOut Done

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