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Embedded Hardware and Software Self-Testing Methodologies for Processor Cores. Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen Design Automation Conference, 2000 Page(s): 625~630 Presented by Kao, Chung-Fu. What’s the Problems ? .

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Embedded hardware and software self testing methodologies for processor cores

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores

Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen

Design Automation Conference, 2000

Page(s): 625~630

Presented by

Kao, Chung-Fu

What s the problems
What’s the Problems ? for Processor Cores

  • Current external testers vs. GHz processors.

    • Test speed, equipment cost ($20 million)

  • Does hardware BIST good enough ?

  • Why not Software-Based Self-Testing.

    • Low cost, high-quality self-test methodology

Outline for Processor Cores

  • Introduction

  • Two case: PARWAN and PicoJava-II processor cores

    • Proof that hardware BIST still has many limitations

  • Demonstrate that software-based self-testing methodology is a better approach

  • Experiment and conclusion

Introduction for Processor Cores

  • Generate the required test patterns on-chip

    • At-speed testing, reduce the cost

  • Built-In Self-Test (BIST)

    • Use for memory logic due to regular structure

  • How to test non-memory parts ?

  • Software-based self-testing

Preliminary for Processor Cores

  • The commercial logic BIST tool: LBIST

    • Applying BIST to two processor cores

The design-under-test often has to be modified extensively to be random pattern testable

Case study i parwan
Case Study I: PARWAN for Processor Cores

  • We should modify the design in order to make the application of LBIST effective.

  • Splitting all bi-directional pins into separate I/O pins

  • Replacing all tri-state buffers with selectors

  • Inserting test points to improve the testability of the circuit


LFSR, MISR, boundary scan for Processor Cores

Use test points


* On the modified circuit

** On the modified circuit with test points

Case study ii picojava ii
Case Study II: PicoJava-II for Processor Cores

Software based self testing
Software-Based Self-Testing for Processor Cores

  • Uses a software tester embedded in the processor memory

  • For test generation and test application

  • Advantages

    • Programmability;

    • Flexibility;

    • Generates desirable random test sets on-chip

    • No need of scan chains and boundary scan

The software based self testing methodology
The Software-Based Self-Testing Methodology for Processor Cores

  • The self-testing scheme includes two steps

    • Test preparation step

    • Self-testing step

Step 1 component test preparation
Step 1: Component Test Preparation for Processor Cores

  • The test need of the component by aself-test signature

    • The seed (S)

    • The configuration (C)

    • The number of test patterns to be generated (N)

  • Instruction-based testing

Instruction imposed constraints

in_flag for Processor Cores












Hardware paths involved in testing the SHU

Instruction-Imposed Constraints

  • Spatial constraints

  • Temporal constraints

  • Ex:

  • asl and asr can not be both 1,

  • z and n must be consistent with data_in,

  • v = xor (c, sign_bit (data_in) )

Constraint modeling
Constraint Modeling for Processor Cores

  • Spatial constrain

    • Random patterns used on independent inputs

  • Temporal constrain

    • As figure shown

Step 2 on chip self test
Step 2: On-Chip Self-Test for Processor Cores

  • Uses an embedded software tester for the on-chip generation

Test generation program

external XOR gate for Processor Cores

polynomial = 101 (1+x2)

Seed (011)

Test Generation Program

  • Using pseudo random number generator

  • The S/W program emulating a H/W LFSR (Linear Feedback Shift Register)

Q = S

DoN times


AC = Bitwise-and (C, Q);

New_bit = Parity (AC);

Q = New_bit : (Q >> 1);


Hardware Implementation

Test application program
Test Application Program for Processor Cores

  • Outputs observation

    • Data outputs

    • Status outputs

0 lda addr (y) // load AC

1 add addr (x)

2 sta data_out // store AC

3 lda 11111111

4 brav ifv // branch if overflow

5 and 11110111

6 label ifv brac ifc // branch if carry

7 and 11111011

8 label ifc braz ifz // branch if zero

9 and 11111101

10 label ifz bran ifn // branch if negative

11 and 11111110

12 label ifn sta flag_out

Experimental results

Prepares a VHDL test bench containing the initialized for Processor Coresinstruction memory and data memory

Run the test bench, and captures the input signals to the processor. These are the test vectors to be applied during fault simulation

Experimental Results

  • Test evaluation framework

Experimental results cont d
Experimental Results (cont’d) for Processor Cores

* Test pattern generation program

Conclusion for Processor Cores

  • Demonstrated some of the disadvantages associated with H/W-based BIST tech.

  • We hope that no need to change design when insert the test mechanism.

  • Software-based self-testing tech. had proposed

    • No hardware overhead

    • Save money