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Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

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Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

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  1. Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems Part 3: semantics and synthesis Gérard Berry Chief Scientist www.esterel-technologies.com Gerard.Berry@esterel-technologies.com

  2. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  3. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  4. The Pure Esterel Kernel nothing empty statement pausewait next tick emitSemit S for this instant if S then p else q end test S at this instant suspend p when S stall p for the instant if S p;qstart q when p terminates loop p end restart p when terminated p || qrun p and q concurrently trap T in p end declare exit label T in p exit Texit trap T construct signal S in pend declare S local in p

  5. loop pause end halt = await S = Bootstraping of other statements trap T in ; if S then exit T end end loop pause end

  6. Bootstraping of other statements loop end abort p; loop pause end when S loop p each S = Synthesis algorithms may choose to map statements to circuits directly (for optimization)

  7. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  8. 0 1 ! s s?p,q sp p;q p p| q {p}p k, k > 1 p\s U * The Pure Esterel Kernel nothing pause emit S present S then p else q end suspend p when S p; q loop p end p|| q trap T in p end exit T signal S in p end

  9. Mathematical Semantics • Behavioral Semantics: logical consistency • A signal is present if and only if it is emitted • Reactivity and determinism required • Constructive Semantics: logical constructiveness • Explain why signals are present or absent • Reactivity and determinism implied • Operational Semantics: microsteps Constructive = Operational < Behavioral

  10. completion code emitted signals E’ k p p’ E received signals Broadcasting : E’ E U The Behavioral Semantics 0 : termination 1 : waiting 2 : exiting one trap level 3 : exiting two trap levels k

  11. 0 k k 0 E (for k=0, k=1, k>1) {s} 0 !s 0 E

  12. E’ k p p’ s E E E’ k s ? p, q p’ E F’ l q q’ s E E F’ l s ? p, q q’ E

  13. E’ 0 p p’ E E’ 0 0 s p U E E’ k p p’ k = 0 E E' k s p' s p U U E with s p' = {( s ? 1 , 2) } ; s p' U U *

  14. E’ k p p’ k =0 E E’ k p ; q p ’ ; q E E’ 0 F’ l p p’ q q’ E E E’ U F’ l p ; q q’ E

  15. E’ k F’ l p p’ q q’ E E E’ k p p’ k = 0 E E’ k p p’ ; p * * E E’ U F’ max(k,l) p’ | q’ p | q E

  16. E’ k p p’ k = 1 or k > 2 E E’ k {p} {p’} E E’ k p p’ k = 0 or k = 2 E E’ 0 {p} 0 E k = 1 if k=1, k-1 if k>2

  17. E’ k p p’ E E’ k p' p E 0 = 0 k = k+1 if k >1 1 = 1

  18. E’ U {s} k p p’ s E' s E E U {s} E’ k p \ s p’ \ s E E’ k p p’ E E’ k p \ s p’ \ s E Unique solution => determinism But no solution or several solutions possible!

  19. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  20. Translation into Boolean Circuits Initiated by J. Vuillemin and P. Bertin (DEC) Esterel v4 (1992) - acyclic circuits Limited causality - users complain! Esterel v5 (1996) - cyclic circuits Constructive causality Almost structural but reincarnation difficult

  21. Each statement p corresponds to a box: Basic syntax directed translation scheme • EandE’:signals received and emitted • GO: startp(first cycle) • RES:continuefrom the previous state • SUSP: freeze for a cycle (keep registers) • KILL : reset registers • SEL: at least one register set = statement alive • Ki : 1-hot encoded completion code • K0: normal terminate • K1: pause for a cycle • K2,K3,… - exit enclosing traps E E' SEL GO K0 RES p K1 SUSP K2 KILL ... Exclusive relation: GO # RES # SUSP

  22. GO K1 RES SUSP K0 KILL SEL Circuit for 1 (pause)

  23. E E' s E E' GO GO SEL SEL RES RES K0 K0 p SUSP SUSP K1 K1 KILL KILL K2 K2 ... Circuit for abort p when s

  24. Circuit for sequencing P; Q

  25. Circuit for P||Q

  26. The parallel synchronizer

  27. E E' s E E' GO GO SEL SEL RES RES K0 K0 p SUSP SUSP K1 K1 KILL KILL K2 K2 ... Circuit for abort p when s

  28. Syntax directed translation by example loop abort {awaitAddr || awaitData} ; callWrite (?Addr, ?Data) ; awaitLatency times tick whenReplay end loop Addr GO SEL RES K0

  29. Syntax directed translation by example Addr GO loop abort {awaitAddr || awaitData} ; callWrite (?Addr, ?Data) ; awaitLatencytick whenReplay end loop RES Data

  30. Syntax directed translation by example Addr loop abort {awaitAddr || awaitData} ; callWrite (?Addr, ?Data) ; awaitLatencytick whenReplay end loop GO SEL RES K0 Data Write(…)

  31. Syntax directed translation by example Addr GO SEL RES K0 Data Write(…) C:=Latency DSZ C

  32. Syntax directed translation by example Addr 0 1 Replay Data Write(…) C:=Latency DSZ C

  33. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  34. Sequential Optimization Scheme • Build the netlist • good start, but too fat • Remove redundant registers • not too many, just the fat • syntactic don’t care (group-hot) • reachable states • Optimize the logic • depthfor hardware • areafor software Implementation : SIS 1.3 + TiGeR

  35. Automata to circuits, bad solution 1 one-hot encoding B Lots of registers, lots of gates…...

  36. Automata to circuits, bad solution 2 dense encoding • for n states, log(n) registers are enough • but combinational logic needs to encode / decode states • 2log(n) = n combinational gates worst case • + very sensitive to the actual encoding of states • only n! permutations to check... • no good heuristics….

  37. I O combinational logic state registers R

  38. Structural State Encoding • Minimal encoding : log n regs. • does not scale - logic explosion • Structural encoding from Esterel • one register per explicit delay • does scale • good register / logic compromize • easy to optimize • 1-hot encoding : n regs. • does not scale - register explosion

  39. Sequential optimization algorithms • Detect registers that are always equal or opposite • Detect registers that are functions of other registers for all reachable states => logic • Multiplex registers that are exclusive over time On large hierarchical FSMs very good register / logic ratio

  40. Esterel : Write Things Once loop [ await A || await B ] ; emit O each R One register per explicit delay

  41. 1 0 1 0 1 1 0 1 0 0 0 0 1 1 1 0 Group-hot state encoding Concurrent threads => independent groups sequencing => group-hot 1-hot: 4bits Log: 2bits group-hot: 3bits - scales best. loop [ await A || awaitB ] ; emit O each R A? B? R? O!

  42. Efficient calculation of reachable states F R0 = 0 R1 = R0 U F(R0) R2 = R1 U F(R1) .... RSS = U Ri compute using BDDs but.... BDD(F) explodes! key: use Ri as a simplifier for BDD(F) (Madre, Coudert, Touati)

  43. Ri G smaller BDD G = F on Ri Ri+1 = Ri U G(Ri) BDD simplification by care sets F E D Ri+1 = Ri U F(Ri)

  44. RSS G smaller, faster G = F on RSS Logic simplification by care sets F E D

  45. Functional redundancy elimination Register Ri is cheaplyredundant if it can be replaced by a small function of the other registers Necessary and sufficient condition: RSS(Ri0) RSS(Ri 1) Replacement function : eitherRSS(Ri0) or RSS(Ri 1) Good if either function is small

  46. speed optimization WRISTWATCH pi= 8 po=92 nodes= 97 latches=12 lits(sop)= 406 lits(fac)= 366 Total number of levels = 3 area optimization WRISTWATCH pi= 8 po=92 nodes= 98 latches=11 lits(sop)= 195 lits(fac)= 195 Total number of levels = 15 Optimization using SIS initial WRISTWATCH pi= 8 po=92 nodes=462 latches=35 lits(sop)= 990 lits(fac)= 990 Total number of levels = 29

  47. 1 || # # || # Exclusive Latches Multiplexing can replace RSS by ORSS (over-approximation) computed from group-hot serial / parallel structure

  48. demultiplexer Multiplexing registers # || || not necessarily a good idea....

  49. Agenda - Part 3Semantics and Synthesis • The Esterel kernel • Mathematical semantics • Circuit synthesis • Sequential optimization • Software synthesis

  50. Software Compilers • Automata based • Esterel program specifies a finite state machine • Code this FSM in C • Esterel V3 compiler (INRIA/CMA, 1992) • The fastest code, but does not scale • Netlist based • Esterel program can be mapped to logic netlist • Sort the netlist and print as C code: one cycle computation require one pass through the netlist • Esterel v5 compiler • Scales well (linear from the program size), but relatively slow since computes all equations even if not needed in a cycle • V7 extends to arrays with mapping to for loops