1 / 24

Huifang Qin, Kevin Cao, Prof. Jan Rabaey Berkeley Wireless Research Center 1

Outline. Introduction Go low voltage in digital CMOS design! Power Delay Reliability Memory side Results from SRAM leakage control test chip Data Retention Voltage (DRV) Timing overhead in modes switching Leakage saving in low voltage standby Low standby supply voltage generation L

jude
Download Presentation

Huifang Qin, Kevin Cao, Prof. Jan Rabaey Berkeley Wireless Research Center 1

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


    1. Huifang Qin, Kevin Cao, Prof. Jan Rabaey Berkeley Wireless Research Center 1/14/ 2002

    2. Outline By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    3. Low Voltage CMOS Design Considerations By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    4. Low Voltage CMOS Design Considerations By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    5. Existing Work and the Goal By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    6. SRAM Chip and Testing By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    7. Switch Capacitor Converter Output By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    8. Switch Capacitor Converter Output By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    9. Dual Supply Scheme 1V / 200mV By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    10. Supply Switching Timing Overhead This is the block diagram of the sensor node architecture, as an example of the event driven system.This is the block diagram of the sensor node architecture, as an example of the event driven system.

    11. State 0 Preservation The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication. The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication.

    12. State 1 Preservation The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication. The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication.

    13. 0.13um SRAM Leakage Vs. Vdd The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication. The sessions are defined as the communication between blocks. The goal is to help designers design blocks in isolation with communication ports. The DLL doesn't care where it's outputs are connected, it just needs to know that it wants to send data out of port A or port B. The power manager is programmed to know what is actually connected to those ports. And the ports then work with the PM to decide the right action to carry out the communication.

    14. Outline By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

    15. Variations in the Nanometer Regime

    16. Technology Trend ITRS predicts constant process deviations However, process control is much more costly Operation-caused variations (Vdd, coupling noise, Temp.) keep increasing

    17. Simulation Methodology Monte Carlo analysis is more accurate than worst case analysis Capable to handle correlations Fast enough for simple critical path structure Interconnect coupling modeled

    18. CMOS Inv. Delay Distribution Off Gaussian

    19. CMOS Inv. Delay Distribution Off Gaussian

    20. Lognormal Model Fitting the Delay Distr.

    21. Lognormal Model Proved Efficient on 130nm / 70nm Inverter Delay Distribution

    23. Why the Lognormal?

    24. How should we model more complicated gates / data paths in the future?

    25. Future Work By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.By default the system is sleeping. Then blocks are woken up one by one with the event requests. To design a event driven system, first we need to fit the event driven model to the design. Well use the sensor network design as an example through out this talk because its a good match of the event driven model. How its event driven? First on the node scale .. Also inside the chip the blocks can also be modeled at event driven operation sequence.

More Related