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Power Supply Controller Architecture

Power Supply Controller Architecture. Yuke Tian Control Group, Accelerator Division Photon Science Directory Brookhaven National Lab. EPICS Collaboration Meeting, BNL, 2010. Outline. 1. NSLS-II power supply control system System overview  Current regulator

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Power Supply Controller Architecture

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  1. Power Supply Controller Architecture Yuke Tian Control Group, Accelerator Division Photon Science Directory Brookhaven National Lab EPICS Collaboration Meeting, BNL, 2010

  2. Outline 1. NSLS-II power supply control system System overview  Current regulator  Power supply interface (PSI)  Power supply controller (PSC) 2. NSLS-II power supply controller architecture PSC system architecture Diagnostics with DDR2 100Mbps serial device link Embedded microblaze Interface with PSI Remote reprogram capability 3. Progress 4. Summary EPICS Collaboration Meeting, BNL, 2010

  3. NSLS-II power supply control system — System overview Magnets and Power Supplies in Storage Ring EPICS Collaboration Meeting, BNL, 2010

  4. NSLS-II power supply control system — System overview • Provide 3.8ppm current resolution and less than 25ppm long term stability. • Flexible setpoint for one power supply or synchronous setpoints for a group power supplies. • 10KHz fast orbit correction operation. • Up to 10Hz slow orbit correction operation. • Detect and set machine protection errors in 2 ms. • Build-in power supply ripple detections. • At least 10 seconds circular buffer to transient waveform recorder. • Provide at lease 1 second Booster PS synchronous ramping function. EPICS Collaboration Meeting, BNL, 2010

  5. NSLS-II power supply control system — System overview DC and slow magnet power supply control EPICS Collaboration Meeting, BNL, 2010

  6. NSLS-II power supply control system — System overview Fast and slow corrector magnet power supply control EPICS Collaboration Meeting, BNL, 2010

  7. NSLS-II power supply control system — Current regulator Klixon EPICS Collaboration Meeting, BNL, 2010

  8. NSLS-II power supply control system — Power supply interface (PSI) EPICS Collaboration Meeting, BNL, 2010

  9. NSLS-II power supply control system — Power supply controller (PSC) EPICS Collaboration Meeting, BNL, 2010

  10. NSLS-II power supply controller architecture — PSC system architecture EPICS Collaboration Meeting, BNL, 2010

  11. NSLS-II power supply controller architecture — PSC system architecture 3 6 4 1 7 7a 8a 5 2 8b 1 = JTAG connectors – Programming to FPGA and CPLD. 2 = RS232 port – Communication to PC for diagnostic and software development. 3 = DDR2 memory modules – PS diagnostic data, CPU memory. 4 = SDI connectors – Communication between PSC master (or cell controller) and PSC slaves. 5 = Fiber transceiver – Communication with PSI. 6 = Ethernet connector – Communication to EPICS IOC for PSC master. 7 = FPGA (Spartan3A) 8 = CPLD(8a) & SPI memory(8b) – Dual boot and remote programming functions. EPICS Collaboration Meeting, BNL, 2010

  12. NSLS-II power supply controller architecture — Diagnostics with DDR2 • One signal chip (Hynix H5PS2G, $20/each) provide 256MB DDR2 memory for each power supply controller. There are many benefits to have large memory on PSC. • Each PSC is used as transient waveform recorder to save at least 10 seconds diagnostics data for different power supply readbacks. • DDR2 is used to save large ramping function for ramping accelerator machine. For NSLS-II, the ramping function consists of 10K setpoints. • DDR2 is used as memory for embedded microprocessor (Xilinx Microblaze). It can be used for code, data, head and stack section. EPICS Collaboration Meeting, BNL, 2010

  13. NSLS-II power supply controller architecture — 100Mbps serial device interface Control system data communication question ? How to establish a communication between modules that is: • Reliable and redundant 2. Deterministic 3. Extendable and easy to deploy 4. Low cost (for NSLS-II, about 1000 PSCs) Choices: • VME: • High cost, parallel bus limit its speed, not easy extendable • General Ethernet communication running TCP/IP: • Good for most requirements. But it is not deterministic. EPICS Collaboration Meeting, BNL, 2010

  14. NSLS-II power supply controller architecture — 100Mbps serial device interface Master (PSC master, Cell controller) PSC PSC PSC PSC TX RX TX RX TX RX TX RX RX TX RX TX RX TX RX TX RX TX RX TX TX RX TX RX PSC PSC Power supply SDI link RX TX RX TX TX RX PSC PSC PSC PSC TX RX TX RX TX TX RX RX RX TX RX RX TX TX EPICS Collaboration Meeting, BNL, 2010

  15. NSLS-II power supply controller architecture — 100Mbps serial device interface • 100Mbps serial device interface (SDI) provides a solution for power supply data communication between various systems. It uses the commonly available CAT5 cable, RJ45 connector, Ethernet PHY chip (National, DP83849, $6/each), and FPGA logic design to establish a 100Mbps communication between systems. • Data is transferred only through Ethernet PHY layer and the communication is deterministic. • Each node just needs to communicate with its two neighbors through two CAT5 network cable. This minimizes the cabling work and it is extendable. EPICS Collaboration Meeting, BNL, 2010

  16. NSLS-II power supply controller architecture — Embedded microblaze • For master PSC or cell controller, embedded microblaze provides TCP/IP communication with EPICS IOC. • Embedded microblaze also provide flexible functions for power supply control such as ripple detection, ramping function generation etc. • For Xilinx FPGA, the easiest way to read/write data to/from DDR2 memory is through multiport memory controller (MPMC), which requires a embedded microblaze. • Xilinx bootloader requires embedded microblaze. • It is a free 32 bit RICS embeded CPU that runing between 50MHz to 200MHz (depending on FPGA chips). EPICS Collaboration Meeting, BNL, 2010

  17. NSLS-II power supply controller architecture — Interface with PSI • NSLS-II PSC communicates with power supply interface (PSI) through a low cost 50Mbps fiber link. The fiber link provide the electrical isolation between PSC and PSI. For some accelerators, the power supply has several KV bias and fiber isolation between system is necessary. • A on board data clock recovery chip (DCR) with PLL is used to recover the receiving data and clock. All setpoints and readbacks have accociated CRC checking. EPICS Collaboration Meeting, BNL, 2010

  18. NSLS-II power supply controller architecture — Remote reprogram capability • For large quantities of PSC, it is desirable to have the remote reprogram capability build-in so that upgrade can be done automatically. NSLS-II PSC is designed to have such function. EPICS Collaboration Meeting, BNL, 2010

  19. Progress • All NSLS-II power supply control subsystem (PSC, PSI and current regulator) prototype design is done and tested. The production procurement (total of about $4 million) is in progress. • FPGA firmware and EPICS software development for different applications (such as Booster application, fast orbit feedback) is underway. EPICS Collaboration Meeting, BNL, 2010

  20. Progress — current regulator Prototype low noise current regulator. Firmware is completed and tested for electronic adjustment of offset and gain of critical circuits. Diagnostic signals brought out to both slow high precision DVM and fast ADC on PSI. Tests show < 5ppm current stability for > 1 hour. Testing has shown this card meets all stability and noise requirements. Maximize reliability through component selection and derating 4 1 2 1 5 3 1 6 1= Industrial switch mode low level power supplies 2= Low noise power conditioning filters 3= Microcontroller used for state control & interlocks 4= Precision burden resistors to convert current from DCCT to voltage 5= High gain low noise analog current regulator 6= AC power entry module with line filter EPICS Collaboration Meeting, BNL, 2010

  21. Progress— PSI • Ten prototypes built by vendor • - PCB assembled by machine • PS Current Setpoint • - One 18-bit DAC (up to 100 kHz) • Diagnostic signals • - Nine 16 Bit ADCs • - 3 High Precision ADC, one of them can go up to 100 kHz. • - 6 Low Precision ADC • State Control & Status • - 8 Digital Outputs • -16 Digital Inputs • Fiber Optic Data Transfer to PSC at 10 kHz frame rate. • Slow Serial Port to RCU. • Tests show < 5ppm DAC stability for > 1 hour. 3 4 1 2 5 6 1 = Switch mode low level power supplies 2 = Low noise power conditioning filters 3 = FPGA used to convert fiber optic data to DACs & ADCs 4 = Micro-controller used for temperature Control of DACs 5 = Temperature stabilized DAC daughter board 6 = Analog signal connector to Current Regulator Card Recent tests have shown a much lower temperature coefficient that originally planed for the DAC. New design will not need the DAC temperature controlled. Also we have decided to use Analog Device’s latest 20bit DAC (0.05ppm/C drift, 1ppm resolution). EPICS Collaboration Meeting, BNL, 2010

  22. Progress— PSI Single-Channel PSI Front Panel Single-Channel PSI Rear Panel Dual-Channel PSI Front Panel Dual-Channel PSI Rear Panel EPICS Collaboration Meeting, BNL, 2010

  23. Progress— PSC FRONT BOARD SLOT 1-21 Chassis takes advantage of front to back cooling PSC Crate Front View REAR SLOT 1-20 REAR SLOT 21 REAR BOARD FRONT SLOT 1-21 PSC Crate Rear View EPICS Collaboration Meeting, BNL, 2010

  24. Current drift data for 90 minutes Progress— Current drift EPICS Collaboration Meeting, BNL, 2010

  25. Current setpoint resolution Test Progress— Resulotion EPICS Collaboration Meeting, BNL, 2010

  26. Summary NSLS-II power supply control system’s performance is proven better than the requirements. It provides 1ppm resolution and 1ppm long term current stability. NSLS-II PSC system is designed to have many features for power supply control and diagnostics. It is easy to integrated with other system. NSLS-II power supply hardware, firmware and software design is fully open to the community and we welcome other facility to apply our design in their system. EPICS Collaboration Meeting, BNL, 2010

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