LOGIC DESIGN

# LOGIC DESIGN

## LOGIC DESIGN

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##### Presentation Transcript

1. LOGIC DESIGN SEUENTIAL CIRCUITS MODELLING AND MEMORY ELEMENTS Upgrade 2: June 2012 Ertuğrul Eriş

2. EE33201 COURSE ASSESMENT MATRIX

3. COMBINATONAL VS SEQUENTIAL CIRCUITS • 24 23 22 21 20 • t4 t3 t2 t1 t0 carry(elde)11000 • input(12) x1 0 1 1 0 0 • input(14) x20 1 1 1 0 • output(26) z 1 1 0 1 0 Ertuğrul Eriş

4. SEQUENTIAL CIRCUITS MODELLING • Mathematical Madelling • State Table • State Diagram Ertuğrul Eriş

5. ARDIŞIL DEVRELERİN GENEL YAPISI Ertuğrul Eriş

6. GENERAL STRUCTURE OF SEQUENTIAL CIRCUITS Ertuğrul Eriş

7. MATHEMATICAL MODEL • Independent variables • Input variables, (x1, …xn) • State variables (y1,…..yr) • N= number of states, n=number of state variables • n=log2N • N=2n • Dependent variables • Next state functions (Y1,Y2,…Yr) • Output functions (z1,z2,….zm) • Serial Adder • Yt+1= y' x1x2+y x'1x2+y x1x'2,+y x1x2 ve • Z = y' x'1,x2+y' x1x'2,+y x'1x'2+y x1x2 Ertuğrul Eriş

8. STATE TABLE Ertuğrul Eriş

9. STATE DIAGRAM Ertuğrul Eriş

10. BLOK DIAGRAM OF SEQUENTIAL CIRCUIT Ertuğrul Eriş

11. SYNCHRONOUS CLOCKED SEQUENTIAL CIRCUIT Ertuğrul Eriş

12. GENERAL STRUCTURE OF SEQUENTIAL CIRCUITS Ertuğrul Eriş

13. ARDIŞIL DEVRE GENEL YAPISI Ertuğrul Eriş

14. SR MEMORY ELEMENT Ertuğrul Eriş

15. ANALYSIS OF SR MEMORY ELEMENT t v Ertuğrul Eriş

16. S*R* LATCH WITH NAND GATES In Mano NAND gates SR lacth, my notes S*R* Latch S*R* S* R* Ertuğrul Eriş

17. MEMORY ELEMENTS PROBLEMS AND THEIR SOLUTIONS • In case of simultenous chage occur on both input varibles (for example 01→ 10), (00 or 11) forbidden inputs might be applied due to delays • Solution • 00(11, NAND) input (ineffective input)application between the inputs 01→00(11 NAND)→10, • Additional «CLOCK» Input Ertuğrul Eriş

18. TWO VARIABLE’S (SR) VALUES CHANGE SIMULTANOUSLY Ertuğrul Eriş

19. SR-LATCH MEMORY ELEMENT Memory element with clock(enable) input S* R* Ertuğrul Eriş

20. D-DELAY(GEÇİKME) LATCH MEMORY ELEMENT S* R* Enable/clock. Could there be a delay memory element without a clock input? Ertuğrul Eriş

21. JK- MEMORY LATCH Toggling for (11) input, how solved? Ertuğrul Eriş

22. T- MEMORY ELEMENT LATCH Toggling for (1) input, how solved? Ertuğrul Eriş

23. TOGGLING PROBLEM FOR JK AND T MEMORY ELEMENTS • During the clock pulse duration T and JK memory elements toggle many times for the inputs (1) and (11) rspectively. • Clock pulse duration becomes problem, • Solution • Edge triggered memory elements «Flip flops» Ertuğrul Eriş

24. PULSE DURATION PROBLEM FOR SEQUENTIAL CIRCUITS Combinatinal circuit delay vs pulse duration SOLUTION: EDGE TRIGGERED MEMORY ELEMENT «FLIP FLOP» Ertuğrul Eriş

25. LATCH vs FLIP FLOP • LATCH • No clock at all, • Level clock (Enable) • FLIP FLOP • EDGE-TRIGGERED-CLOCK-INPUT MEMORY ELEMENT Ertuğrul Eriş

26. CLOCK RESPONSE IN LATCH AND FLIP FLOP Değişim yok Değişim olduğu an Ertuğrul Eriş

27. T FLIP FLOP Ertuğrul Eriş

28. DIFFERENT REPRESENTATION OF FLIP FLOP’s DEFINITION RELATION(CHARACTERISTIC TABLES) Ertuğrul Eriş

29. MASTER-SLAVE D FLIP FLOP Number of elements and delay comparison? Ertuğrul Eriş

30. MASTER SLAVE SR MEMORY ELEMENT Maliyet ve geçikme karşılaştırması? Ertuğrul Eriş

31. D-TYPE POSITIVE-EDGE-TRIGGERED FLIP FLOP S* R* Number of gates and delay comparison? Ertuğrul Eriş

32. D-TYPE POSITIVE-EDGE-TRIGGERED FLIP FLOP S* R* Ertuğrul Eriş

33. SETLING/HLDING TIMES Oturma zamanı: Setling time Tutma zamanı: Holding time Ertuğrul Eriş

34. GRAPHIC SYMBOL Ertuğrul Eriş

35. D FLIP FLOP WITH ASYNCHRONOUS RESET S* R* Ertuğrul Eriş

36. COMMERCIAL JK MEMORY ELEMENT Ertuğrul Eriş

37. SEQUENTIAL CIRCUITS CLASSIFICATION SEQUENTIAL CIRCUIT SYNCRONOUS SEQUENTIAL CIRCUITS (with clok) ASYNCRONOUS SEQUENTIAL CIRCUITS (Without clock) Fundemental mode Pulse mode mode Ertuğrul Eriş

38. PROGRAM DESIGN DEPT, PROGRAM G R A D U A T E S T U D E N T STUDENT P R OG R A M O U T C O M E S PROGRAM OUTCOMES P R OG R A M O U T C O M E S STATE, ENTREPRENEUR FIELD QALIFICATIONS EU/NATIONAL QUALIFICATIONS KNOWLEDGE SKILLS COMPETENCES NEWCOMERSTUDENT ORIENTIATION GOVERNANCE Std. questionnaire ALUMNI, PARENTS ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY NGO STUDENT, ??? CIRCICULUM ??? INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

39. BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001) !!Listening !! Doesn’t exits in the original!!! http://www.learningandteaching.info/learning/bloomtax.htm Ertuğrul Eriş

40. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY Ertuğrul Eriş

41. COURSE ASSESMENT MATRIX LEARNING OUTCOMES Ertuğrul Eriş