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Carbon Nanotube FETs: Imperfection-Immune Digital VLSI

Carbon Nanotube FETs: Imperfection-Immune Digital VLSI. Subhasish Mitra H .-S. Philip Wong. Department of EE & Department of CS Stanford University. BIG Promise, Major Obstacles. Mis-positioned CNTs. Metallic CNTs (m-CNTs). Imperfection-immune design essential. 2. A. B. A. B.

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Carbon Nanotube FETs: Imperfection-Immune Digital VLSI

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  1. Carbon Nanotube FETs: Imperfection-Immune Digital VLSI SubhasishMitra H.-S. Philip Wong Department of EE & Department of CS Stanford University

  2. BIG Promise, Major Obstacles Mis-positioned CNTs Metallic CNTs (m-CNTs) Imperfection-immune design essential 2

  3. A B A B Mis-positioned CNT-Immune NAND Grow CNTs Extended gate, contacts Etch gate & CNTs Dope P & N regions Vdd Etched region essential Out Gnd • Arbitrary logic functions • Graph algorithms 3

  4. Most Importantly • VLSI processing • No per-unit customization • VLSI design flow • Immune CNT library 4

  5. m-CNT Processing Options • Grow 0% m-CNTs • Open challenge • Remove m-CNTs after growth • 99.99% • Early attempts inadequate • Correctness, scalability 5

  6. Solution: VMR • VLSI Metallic CNT Removal • Universally effective • All logic designs • VLSI processing & design flows 6

  7. First Wafer-Scale Aligned CNT Growth Quartz wafer with catalyst Aligned CNT growth Quartz wafer with CNTs 99.5% aligned CNTs 20mm Stanford Nanofabrication Facility 7

  8. Wafer-Scale CNT Transfer • Low temperature (90oC – 120oC) Thermal Release Adhesive Tape Beforetransfer After transfer Quartz SiO2/Si 2 µm 2 µm 8

  9. First VLSI Demonstration Mis-positioned CNT-immune NAND, NOR, AND-OR-INV, OR-AND-INV Etched Region NAND pullup 100 50 Current (µA) 0 offoff offon onoff onon AB off = 2V, on = -2V 9

  10. First Experimental Demonstration Imperfection-immune CNT VLSI circuits Arithmetic circuits Storage circuits Adder Sum D-latch 10

  11. First Monolithic CNT 3D ICs 3-layer CNFET inverters 2-layer CNFET XOR Conventional via, NOT TSV 11

  12. CNT Variations Grown CNT density m-CNT-induced Others: diameter, doping, channel length 12

  13. Overcoming CNT Variations Energy cost Upsize High CNT correlation Unique property Special layouts Co-optimized processing Better process Do nothing 0% Yield 0% High 13

  14. Processing & Design Co-Optimization % grown m-CNTs (pm) m-CNT removal (pRm, pRs) Grown CNT density variations (IDC) Special layouts CNFET sizing VMR structure … Optimized Guidelines Noise margin Yield Delay variations 14

  15. Processing & Design Co-Optimization pm = 10%, IDC = 0.5, pRs = 5% 14% 12% 10% pm = 5% Delay penalty 8% IDC = 0.25 6% Path A: chirality control pm = 10% 0.1% pRs= 2.5% 4% Path B: count control pm = 10% 5%, IDC = 0.5 0.25, pRs= 5% 2.5% 2% 0% 0% 1% 2% 3% 4% 5% Energy penalty Example: OpenSPARC T2 “exu” unit at 16nm 15

  16. Significant Experimental Results Sub-10nm CNFET (IBM) Lch = 9nm Vdd = 0.5V SS = 94mV/dec dCNT ~ 1.3nm Pitch normalized Contributor: A. Franklin(IBM) 16

  17. Significant Experimental Results 400mV Complementary Inverter (Peking U.) Gate length = 1mm Gain = 34 dCNT ~ 1.8nm CV2 ~ 27pJ (Projected: 0.5pJ for 20nm gate length) Single CNT Contributor: LM Peng(Peking U.) 17

  18. Significant Experimental Results Increased CNT Density Target: 100 – 200 CNTs / mm 1. Growth / transfer:  Good alignment,  density variations challenging CNT multiple transfer: (Stanford) Recent News: 100 CNTs / mm (Rogers, UIUC, in press) 2. Dispersed from solution: Great recent progress (IBM, unpublished) Up to 10 CNTs / mm, good alignment, consistent pitch Contributors: W. Haensch (IBM), J. Rogers (UIUC) 18

  19. Significant Experimental Results Semiconducting CNTs (s-CNTs) Target: s-CNTs > 99.9999% 1. (In-place) m-CNT removal:  99.99% removed,  CNT count variations VMR (Stanford) 99.99% m-CNTs, 5% s-CNTs removed Rogers, UIUC Alternative to electrical breakdown (in press) m-CNT electrical breakdown 2. Sort & place: Great recent progress (IBM, unpublished) 99.4% s-CNTs Contributors: W. Haensch (IBM), J. Rogers (UIUC) 19

  20. Significant Experimental Results Imperfection-immune VLSI (Stanford) D-latch Adder Wafer-scale VLSI integration Yield: CNFETs (99%), … Issues explainable: non-ideal litho, … 20

  21. Summary More details: NIST CNFET workshop report (Sept. 6, 2012) • Significant CNFET progress • Imperfection-immune design essential • New solutions: elegantly simple, practical • Next challenge • Energy-efficient CNFET digital systems 21

  22. Next Steps • CNT material • High density, minimize m-CNTs • Quickly quantify purity • Device • Doping: n/p, stable, controllable • Low contact resistance • Thin gate dielectrics, passivation (hysteresis) 22

  23. Next Steps • Design • Variability • Quantify, overcome • Unique CNT properties (e.g., correlation) • Material, device, design co-optimization • Monolithic 3D: new opportunity ? 23

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