Timing verification of vlsi circuits
Download
1 / 24

Timing Verification of VLSI Circuits - PowerPoint PPT Presentation


  • 106 Views
  • Updated On :

Timing Verification of VLSI Circuits. Professor Weiping Shi http://ece.tamu.edu/~wshi/689.html. I. Introduction. What is EDA? Technology trend Design flow Timing verification flow. Technology Trend. International Technology Roadmap for Semiconductors (ITRS)

Related searches for Timing Verification of VLSI Circuits

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Timing Verification of VLSI Circuits' - jihan


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Timing verification of vlsi circuits l.jpg

Timing Verification of VLSI Circuits

Professor Weiping Shi

http://ece.tamu.edu/~wshi/689.html

ELEN 689


I introduction l.jpg
I. Introduction

  • What is EDA?

  • Technology trend

  • Design flow

  • Timing verification flow

ELEN 689


Technology trend l.jpg
Technology Trend

  • International Technology Roadmap for Semiconductors (ITRS)

  • World-wide and industry-wide cooperation since 1992

  • Consensus on R&D needs out to a 15 year horizon

ELEN 689



Implication l.jpg
Implication

  • Signal propagation becomes more difficult due to increasing capacitive and inductive coupling

  • Signal integrity degrades and cause both timing uncertainty and potential logic errors

ELEN 689


Implication6 l.jpg
Implication

  • Testing

    • Decreasing pin/gate ratio

    • Delay fault v.s. stack-at fault

  • Low power

    • Heat already a big problem

    • Wireless applications

  • More…

ELEN 689


Mpu asic design flow l.jpg
MPU/ASIC Design Flow

Design Spec

Behavioral

Design

Verify Function

Logic

Synthesis

Verify Function

Physical

Synthesis

Verify Timing

and Function

ELEN 689


Timing verification l.jpg
Timing Verification

  • Synthesized circuits meet timing constraints

    • Post-synthesis verification

      • Use simple estimation such as unit delay

    • Post-layout verification

      • Use accurate interconnect and gate parasitic

  • Design closure

ELEN 689


Design closure l.jpg
Design Closure

Bad

Timing Verification

Number of Paths

Violating Timing

Constraints

Good

Timing Verification

Iterations

ELEN 689


What to verify l.jpg
What to Verify?

  • Synchronous circuit and scan design

    • Combinational circuit between flip-flops

  • Setup time, hold time, clock skew, etc

Combinational

Circuit

clock

ELEN 689


Setup time violation l.jpg
Setup Time Violation

  • Setup time constraint of a flip-flop specifies a time interval before the active edge of clock

  • Data must arrive before the interval

Clock

Data

Data

OK

Clock

Data

Violation

ELEN 689


Hold time violation l.jpg
Hold Time Violation

  • Hold time constraint of a flip-flop specifies an interval after the active edge of clock

  • Data must be stable in the interval

Clock

Data

Data

Violation

Clock

Data

OK

ELEN 689


Clock skew l.jpg
Clock Skew

  • Signal skew is the arriving time difference between two signals

  • Clock skew between any two leaves must be within the requirement

ELEN 689


Timing verification flow l.jpg
Timing Verification Flow

Layout

(gds2, LEF/DEF)

Cell Library

Netlist

Interconnect Parasitic Extraction

Model Order Reduction

Delay Evaluation

Paths Violate

Timing Constrains

Timing Analysis

ELEN 689


Example l.jpg
Example

a

y

b

XOR

NAND

NAND

b

a

y

Layout

Synthesis

ELEN 689


Step 1 parasitic extraction l.jpg
Step 1. Parasitic Extraction

s1

XOR

NAND

NAND

s2

a

Distributed RC

R1 R2 R3 : parasitic res

C1 C2 C3 : parasitic cap

Cxor Cnand: gate sink cap

R1

Cnand

Cxor

R2

R3

a

s1

s2

Parasitic

Extraction

or each net

C3

C1

C2

ELEN 689


Step 2 model order reduction l.jpg
Step 2. Model Order Reduction

s1

s2

R1

Cnand

Cxor

R2

R3

a

s1

s2

transfer

functions

C3

C1

C2

h1

s1

h2

s2

a

 load

Model Order

Reduction

ELEN 689


Step 3 delay evaluation l.jpg
Step 3. Delay Evaluation

50% buffer-to-buffer

delay at s1

Buffer-to-buffer Delay:

Time for signal to travel

from input pin of a gate

to input pin of next gate

h1

s1

h2

s2

a

50% buffer-to-buffer

delay at s2

ELEN 689


Step 4 timing verification l.jpg
Step 4. Timing Verification

  • Dynamic

    • Input vector based

    • Expensive when circuit is large

  • Static

    • Independent of input vectors

    • Critical path search

    • Fast, but may overestimate

ELEN 689


Signal coupling l.jpg
Signal Coupling

Coupling Capacitance

Noise

ELEN 689


Crosstalk l.jpg
Crosstalk

  • Cross talk affects delay

01

nominal delay

0

01

delay increased

10

01

delay reduced

01

ELEN 689


Verification and testing l.jpg
Verification and Testing

  • Timing verification identifies paths that violate timing constraints

  • Timing verification also identifies paths are likely violations

    • A near violation can be a true violation under combination of defects, process variations and signal coupling

    • Delay fault testing

ELEN 689


Conclusion l.jpg
Conclusion

  • Technology trend decides important and urgent areas of research

  • Timing verification is a central part of design cycle, and directly affects design cycle and time to market

  • Timing verification for next generation VLSI circuits is increasingly important

ELEN 689


Assignments 1 l.jpg
Assignments #1

  • Read ITRS (http://public.itrs.net/) and for the area of your interest, identify issues that are important

  • Go to MOSIS (http://www.mosis.com) and check their technology file, SPICE models and design rules

ELEN 689


ad