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332:578 Deep Submicron VLSI Design Lecture 13 Dynamic Flip-Flops, Latches, Clocking, and Time Borrowing. David Harris and Mike Bushnell Harvey Mudd College and Rutgers University Spring 2005. Outline. Clocking and CMOS Latches Time Borrowing Two-Phase Clocking Summary.

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332:578 Deep SubmicronVLSI DesignLecture 13Dynamic Flip-Flops, Latches, Clocking, and Time Borrowing

David Harris and Mike Bushnell

Harvey Mudd College and Rutgers University

Spring 2005

Deep Submicron VLSI Des. Lec. 13

outline
Outline
  • Clocking and CMOS Latches
  • Time Borrowing
  • Two-Phase Clocking
  • Summary

Material from: CMOS VLSI Design,

by Weste and Harris, Addison-Wesley, 2005

Deep Submicron VLSI Des. Lec. 13

terminology
Terminology
  • Tokens – held by memory elements (flip-flops and latches)
  • Flip-flops perform sequencing – distinguish current token from previous token
    • Add extra delay – called sequencing overhead
  • Static storage – has feedback to retain output indefinitely
  • Dynamic storage – maintains value as C charge that leaks away if not refreshed

Deep Submicron VLSI Des. Lec. 13

max delay constraints
Max-Delay Constraints
  • Latch sequencing overhead reduces time for combinational logic to compute
  • When comb. Logic delay too great, have setup time failure or max-delay failure
  • Sample wrong value into flip-flop
  • Fix by using faster logic or lengthening clock period

Deep Submicron VLSI Des. Lec. 13

max delay constraint
Max-delay Constraint

Deep Submicron VLSI Des. Lec. 13

constraints with 2 phase latches
Constraints with 2-phase Latches

Deep Submicron VLSI Des. Lec. 13

pulsed latches
Pulsed Latches
  • Only one latch is in critical path
  • If pulse narrower than tsetup, data must set up before pulse rises
  • If pulse wide enough to hide setup time, sequencing overhead is just one latch delay
  • Last expression is sequencing overhead

Deep Submicron VLSI Des. Lec. 13

pulsed latches8
Pulsed Latches

Deep Submicron VLSI Des. Lec. 13

min delay constraints
Min-delay Constraints
  • If hold time large and contamination delay small
    • Data incorrectly goes through 2 successive elements on one clock edge, corrupting system state
    • Race condition, hold time failure, or min-delay failure

Deep Submicron VLSI Des. Lec. 13

min delay constraints10
Min-delay Constraints

Deep Submicron VLSI Des. Lec. 13

min delay
Min-delay
  • If flip-flop contamination delay > hold time
    • Can safely use back-to-back flip-flops
    • Otherwise:
      • Must add delay between FFs (with buffer)
      • Use special slow FFs
    • Example: Testing scan chain

Deep Submicron VLSI Des. Lec. 13

min delay12
Min-delay
  • By making tnonoverlap large enough, avoid hold time failure
  • Hard to generate and distribute non-overlapping clocks at high speed
  • Instead, use clock and its complement
    • tnonoverlap = 0
    • Same contamination delay constraint between latches and flip-flops

Deep Submicron VLSI Des. Lec. 13

min delay constraint
Min-delay Constraint

Deep Submicron VLSI Des. Lec. 13

confusing
Confusing
  • Contamination delay constraint applies to:
    • Each logic phase for latch-based systems
    • Entire cycle of logic for flip-flops
    • Latches require 2 X contamination delay of flip-flops
  • Note: flip-flop has internal race between two latches

Deep Submicron VLSI Des. Lec. 13

pulsed latch min delay constraints
Pulsed Latch Min-delay Constraints

Deep Submicron VLSI Des. Lec. 13

time borrowing
Time Borrowing
  • In a flop-based system:
    • Data launches on one rising edge
    • Must setup before next rising edge
    • If it arrives late, system fails
    • If it arrives early, time is wasted
    • Flops have hard edges
  • In a latch-based system
    • Data can pass through latch while transparent
    • Long cycle of logic can borrow time into next
    • As long as each loop completes in one cycle

Deep Submicron VLSI Des. Lec. 13

time borrowing example
Time Borrowing Example

Deep Submicron VLSI Des. Lec. 13

time borrowing18
Time Borrowing
  • Example:
    • Pipelined CPU – ALU must complete operation and bypass result back to ALU for use by a dependent instruction
  • Most critical paths are in self-bypass loops

Deep Submicron VLSI Des. Lec. 13

how much borrowing
How Much Borrowing?

2-Phase Latches

Pulsed Latches

Deep Submicron VLSI Des. Lec. 13

pulsed latches20
Pulsed Latches
  • Time borrowing benefits:
    • Intentional time borrowing – designer can more easily balance logic between half-cycles and pipeline stages
      • Shortens design time – balancing is done during circuit design, rather than requiring microarchitecture changes
    • Opportunistic time borrowing – delays differ between stages in fabricated chip
      • Process & environmental variations & timing model inaccuracies
      • Slow cycles can average out some variation

Deep Submicron VLSI Des. Lec. 13

methodology
Methodology
  • Experienced designers:
    • Forbid intentional time borrowing until chip approaches tapeout
    • Otherwise, designers assume that their pipeline stage can borrow time from adjacent stages
      • Many designers assume this – paths become excessive
      • Problem hidden until full chip timing analysis done
      • Too late to redesign all those paths

Deep Submicron VLSI Des. Lec. 13

clock skew and balanced delay clock generator
Clock Skew and Balanced Delay Clock Generator
  • Custom Design – get rid of clock buffer
    • Problem: Clock Skew
    • Must carefully distribute global clock signals

Deep Submicron VLSI Des. Lec. 13

cvsl style static register
CVSL Style Static Register

Deep Submicron VLSI Des. Lec. 13

ram cell latch
RAM Cell Latch
  • Reduced noise margin

Deep Submicron VLSI Des. Lec. 13

double edge triggered register
Double-Edge Triggered Register

Deep Submicron VLSI Des. Lec. 13

dynamic single clock latches
Dynamic Single Clock Latches

Deep Submicron VLSI Des. Lec. 13

slide27

Dynamic Single Clock Latches

  • Eliminate feedback inverter & transmission gate
    • Reduce # transistors
  • Store latched value on gate C
  • Clock-to-Q delay very small
    • Could be transparent
    • Need sharp anti-phase clocks
    • Use internal clock inverter

Deep Submicron VLSI Des. Lec. 13

single phase dynamic latch clocking
Single-Phase Dynamic Latch Clocking
  • DEC Alpha (a) clocking
  • Must characterize race conditions of latch – needs care
  • For a, clock tr & tf
    • Worked when < 0.8 nsec
    • Failed when 0.8 nsec tr, tf 1.0 nsec

Deep Submicron VLSI Des. Lec. 13

summary
Summary
  • Flip-Flops:
    • Very easy to use, supported by all tools
  • 2-Phase Transparent Latches:
    • Lots of skew tolerance and time borrowing
  • Pulsed Latches:
    • Fast, some skew tolerance & borrow, hold time risk
  • CMOS Latches

Deep Submicron VLSI Des. Lec. 13