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Mixed-Signal Option for the Teradyne Integra J750 Test System
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  1. Mixed-Signal Option for the Teradyne Integra J750 Test System May08-12 Emily Evers Vincent Tai

  2. Definitions • ADC – Analog-to-Digital Converter • DAC – Digital-to-Analog Converter • Op-amp – Operational amplifier • DIB – Device Interface Board • DUT – Device under Test • IG-XL – Software used by Teradyne for the J750 tester • INL – Integral Nonlinearity • DNL – Differential Nonlinearity • IMD – Intermodulation Distortion

  3. Contents • Requirements Specification • Project Plan • Design Method • Engineering Specification • Detailed Design

  4. Problem Statement The Teradyne system has been updated to allow for analog circuits to be tested, but there are no working test procedures for ADC, DAC and Op-Amps.

  5. Daughterboard Socket Converter Teradyne J750 IG-XL Software Concept Sketch

  6. IC Interface Devices IG-XL Software Documentation Testing System block diagram

  7. System Description • Devices • Analog-to-Digital (ADC) • Digital-to-Analog (DAC) • Op-Amp • IC Interface • Device Interface Board (DIB) • Connects daughter board to tester via pogo pins • Daughter Board • Connects device to DIB

  8. System Description • IX-GL Software • Test Plan • Pin and Channel Map • AC and DC Specs • Timing • Pattern • Testing • Documentation

  9. Operating Environment • The room environment needs to be kept at a consistent temperature of 30°C ± 3° • Electrostatic discharge wrist bands must be worn when using the tester • Access code

  10. Users • Electrical and Computer Engineering Faculty • Graduate Students interested in IC testing • Students in EE 418: High Speed System Engineering Measurement and Testing

  11. User Interface • IG-XL software

  12. Functional Requirements • Cookbook be written for the new users • Testing procedures covers the devices: • 2 Analog-to-Digital (ADC) • 2 Digital-to-Analog (DAC) • Op-Amp

  13. Non-Functional Requirements • Consistent temperature of 30°C ± 3° • Electrostatic discharge wrist bands must be worn when using the tester • Documentation in English • Test program for devices and similar ones • Cookbook for specified devices • Easy to trouble shooting

  14. Market Survey • Teradyne website • Previous team’s website • Teradyne lab manuals

  15. Deliverables • DIB and Daughterboard Mapping • IG-XL code for each device • Completed testing for all devices • Documentation for all devices

  16. Work Breakdown structure • Review Status • Previous work • Teradyne Training Material • IC Interface • Daughter Board • DIB

  17. Work Breakdown Structure • Test Plan Development • Create IG-XL code for testing devices • Debug previous code • Add current limits • New test plans • Execute testing • Documentation • Create Mixed-Signal Option Cookbook • Create maps for daughter board, DIB and socket converters • Reporting

  18. Resource Requirements • Resource Team • Faculty Advisor: Dr. Weber • Course Coordinator: Dr. Smith • Team effort

  19. Resource Requirements • Financial requirements

  20. Project Schedule • Deliverable schedules

  21. Project Schedule • Projected Deliverable Schedules

  22. Project schedule

  23. Accomplishment • Interface Mapping • AD 5447 Progress

  24. Accomplishment • D Flip-Flop Test

  25. Risk And Risk Management • Risk: • Problems learning program • Limited team members • Risk Management: • Read Teradyne manuals and previous groups documentation • Time management

  26. Inputs Process Outputs Parts Results Cookbook Input/Output Signals ADC DAC Op-Amp Calculations AD7892 AD7470 AD5440 AD5447 AD823 Hardware ADC & DAC Op-Amp Software Interfaces INL & DNL IG-XL Program J750 Tester DIB Daughterboard Socket converter Bandwidth Offset Voltages Intermodulation Tests Computer Design Method • Top-Down Design

  27. Input Requirements Devices ADC DAC Op-Amp Input Specifications ADC 10 bit 12 bit DAC 10 bit 12 bit Op-Amp High Speed Input Requirements & Specifications

  28. Inputs • Detailed Design • ADC • AD7892 • AD7470 • Op-Amp • AD823 • DAC • AD5447 • AD5440

  29. Inputs • Detailed Design • AD7892 • 12 bit • Runs off of single 5V supply • Signal-to-noise ratio of 70dB • Conversion time of 1.47us • Sampling rate of 500 KSPS • Cost is $15.45

  30. Inputs • Detailed Design • AD7470 • 10 bit • Single volt supply voltage can range from 2.7V to 5.25V • Sampling rate of 1.75 MSPS • Wide input bandwidth • No pipeline delay • Cost is $3.53

  31. Inputs • Detailed Design • AD823 • Houses two amplifiers • 16 MHz rail-to-rail FET amplifier • Cost is $2.63 with free sample available • Operates on single or dual power supply • Drive capability of 500pF

  32. Inputs • Detailed Design • AD5447 • 12 bit • Update rate of 21.3 MSPS • Settling time of 35ns • 10 MHz multiplying bandwidth • Cost is $9.00

  33. Inputs • Detailed Design • AD5440 • 10 bit • Update rate of 21.3 MSPS • Settling time of 35ns • 10 MHz multiplying bandwidth • Cost is $6.90

  34. Requirements Test Results Specifications Input Signals Output Signals Calculations Outputs

  35. ADC HLHLHL HLHLHL DAC Op-Amp Outputs

  36. Outputs • Detailed Design • ADC and DAC • INL • DNL • Op-Amp • Bandwidth • Offset Voltages • Intermodulation Test

  37. Analog Output 0 - 5V Digital Input 0x00 - 0xFF Outputs • Detailed Design • Integral Nonlinearity • Measure of an error of a point with respect of the user defined transfer function INL = Actual Output - Expected Output l l l Actual Output l l Expected Output l l l

  38. Analog Output 0 - 5V Digital Input 0x00 - 0xFF l l Actual Step Size l l Exected Step Size l l DNL=Actual Step Size - Expected Step Size l Outputs • Detailed Design • DNL • Comparison of the step size error of an actual output to the expected output

  39. Outputs • Detailed Design • Bandwidth • Small Signal • Open Loop • Point where the output is equal to 0dB • Closed Loop • Point where there is a drop of 3dB

  40. Outputs • Detailed Design • Bandwidth • Large Signal • Slope of output is called slew rate

  41. Analog Output 0 - 5V Digital Input 0x00 - 0xFF Outputs • Detailed Design • Offset Voltage • Difference between the actual output and the expected output at the zero point l l l l l l Actual Output Expected Output

  42. 0dB MAGNITUDE -60dB 0 50 100 150 200 250 F2 F1 F2 - F1 F2 + F1 FREQUENCY Outputs • Detailed Design • Intermodulation Test • Determines distortion caused by slight variations gain vs. amplitude

  43. Requirements Mixed-Signal Cookbook IG-XL Specifications Mixed-Signal Cookbook Written in English Easy-to-use IG-XL Program Create test programs with adequate commenting User Interface

  44. Requirements IG-XL Specifications Pin & Channel Maps AC & DC Specs Time Sets Levels Test Instances Procedures Flow Table Software

  45. Software • Detailed Design • Data for IG-XL worksheets is gathered from the datasheets for the DUT

  46. AC specs Time Sets Software

  47. Requirements Teradyne J750 Device Interface Computer Specifications DIB Daughterboard Socket Converter Hardware

  48. Hardware • Detailed Design • Create mapping from DIB to DUT • Map DIB to Daughterboard • Map Daughterboard to Socket Converter • Map Socket Converter to DUT

  49. Hardware • Detailed Design • Interface Mapping

  50. Hardware