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Jim Hutchby – SRC

ITRS Spring Public Conference Emerging Research Devices Annecy, France L’Imperial Palace Hotel April 25, 2007. Jim Hutchby – SRC. ITRS Emerging Research Devices Working Group. Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Fujitsu George Bourianoff Intel/SRC

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Jim Hutchby – SRC

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  1. ITRS Spring Public ConferenceEmerging Research DevicesAnnecy, FranceL’Imperial Palace HotelApril 25, 2007 Jim Hutchby – SRC

  2. ITRS Emerging Research Devices Working Group • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Fujitsu • George Bourianoff Intel/SRC • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • U-In Chung Samsung • Philippe Coronel ST Me • Erik DeBenedictis SNL • Simon Deleonibus LETI • Kristin De Meyer IMEC • Mike Forshaw UC London • Christian Gamrat CEA • Mike Garner Intel • Shigenori Hayashi Matsushita • Toshiro Hiramoto U. Tokyo • Dan Herr SRC • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Kohei Itoh Keio U. • Yasuo Inoue Renesas Tech • Seiichiro Kawamura Selete • Hiroshi Kotaki Sharp • Nety Krishna AMAT • Zoran Krivokapic AMD • Phil Kuekes HP • Lou Lome IDA • Hiroshi Mizuta Tokyo Tech • Murali Muralidhar Freescale • Fumiyuki Nihei NEC • Wei-Xin Ni NDL • Tak Ning IBM • Lothar Risch Infineon • Dave Roberts Air Products • Kaushal Singh AMAT • Kentaro Shibahara Hiroshima U. • Thomas Skotnicki ST Me • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Luan Tran Micron • Ken Uchida Toshiba • Yasuo Wada Waseda U. • Rainer Waser RWTH A • Philip Wong Stanford U. • Kojiro Yagami Sony • In-Seok Yeo Samsung • Makoto Yoshimi SOITEC • In-K Yoo SAIT • Peter Zeitzoff Freescale • Yuegang Zhang Intel • Victor Zhirnov SRC

  3. ITRS Emerging Research Architectures Working Group • Tetsuya Asai Hokkaido U. • Ralph Cavin SRC • George Bourianoff Intel • Erik DeBenedictis SNL • Michael Frank AMD • Dan Hammerstrom PSU • Rick Kiehl U. Minn. • Phil Kuekes HP • Lou Lome NASA/JPL • Sadas Shankar Intel • Rainer Waser Aachen U. • Franz Widdershoven NXP • David Yeh SRC/TI • Victor Zhirnov SRC

  4. Create a New Chapter in 2007 Emerging Research DevicesOrganization & Component Tasks (2007) Emerging Research Devices Emerging Materials Emerging Logic and Memory Devices Emerging Architectures

  5. Elements Existing technologies New technologies Beyond CMOS ERD-WG in Japan year Evolution of Extended CMOS

  6. 2005 ITRS ERDEmerging Research Memory Devices Transfer to PIDS

  7. 2007 ITRS ERDCapacitance-based Memory Technologies

  8. 2007 ITRS ERDResistance-based Memory Technologies New to ERD Memory Table

  9. 2005 ITRS ERDEmerging Research Logic Devices

  10. > 20 >16 - 18 >18 - 20 < 16 For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 Critical EvaluationLogic

  11. Logic Device Conclusions • Continued analysis of alternative technology entries likely will continue to yield the same result: • Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels • Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates

  12. Basis of Existing Assessments of Logic Devices A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices) General Purpose Processor MF1 MF2 MF3 MF4 General Purpose Processor MF12 MF5 MF11 MF6 MF10 MF9 MF8 MF7 Supplementing CMOS

  13. Consider new logic technologies that supplement CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices Determine appropriate metric and compare to Si on the specialized application Determine if proposed application contains a standard set of “macro-functions” Understand the performance of the device in terms of its non-linear characteristics Think in terms of heterogeneous co-processors integrated with traditional CPU New focus of Logic Section

  14. Retain present table that evaluates technology entries (TEs) against CMOS devices for Boolean logic Include a second table (new) that evaluates TEs against CMOS for special purpose “macro-functions” e.g. vision processing Think of macro functions being implemented in special purpose co-processors Revise and broaden the Architecture Section to address possible macro functions Consider inclusion of new TEs based on enhanced functionalities in new operations Direction of 2007 chapter

  15. 2005 ITRS ERDEmerging Research Logic Devices Sub- Categorize Molecular and Spin

  16. Spin Domain wall manipulation Ferromagnetic phase change (nano-domains) Spin transport modulation Spin torque transfer Individual and or collective spin manipulation Molecular devices Crossbar coupling elements Molecular logic elements and interconnects Intra molecular logic elements Sub-categories for Spin and molecular devices

  17. Image recognition Speech recognition DSP (cross correlation) Data Mining Optimization Physical simulation Sensory data processing (biological, physical) Image creation Cryptographic analysis Potential Supplemental Applications Can we define a Universal Set of Basic Macrofunctions?

  18. Possible Macrofunctions Recognition Examine a static data array for a specified feature set and compare to a template Mining Finding sets of patterns in a specified pattern stream Synthesis Making predictions based on stored pattern streams Proposed New Focus of Architecture Section Consider device level architectures that optimally organize alternative non-linear devices to supplement CMOS to provide enhanced hardware capability

  19. Emerging Research Architectures CMOL – ‘Molecule on CMOS’ architecture CNN – Cellular Nonlinear Network AMP – Associative Memory Processor GPP – General Purpose Processor FG-MOS – Floating Gate MOS devices SET – single electron transistor MFTD – multiferroic tunnel diode

  20. Scope: Broaden scope to encourage emerging technologies both to supplement CMOS as well as eventually to invent the new “switch”. Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials. Memory Section: Will add NEMS mechanical memory to section. Divide Emerging Memory Tables into Resistive and Capacitive subcategories Update section in 2007. Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function. Create subcategories for key Technology Entries (e.g. Spin & Molecular logic). Re-considering status of candidate Technology Entries. Re-structuring Logic Section via Emerging Logic Workshop in September. Architecture Section: Revise to focus on encouraging research to explore optimal organization of emerging non-linear devices to efficiently realize macro-functions to supplement the CMOS platform technology. Messages

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