Overview

2. Class wiki!!: http://localhost/testwiki/ Note: must login to xilinx.ece.iastate.edu to access Teams Present weeks work on System Generator, and class feedback. High-level intro to FPGAs abbreviated week one CPRE 583 IP Core integration from System Generator Overview

3. Help share discoveries, and solutions with the rest of the class, and future classes You can (and are encouraged to) edit Class Wiki

4. What did you work on? What issues did you come across? Feedback from class Team Presentations

5. Logic Interconnect/Routing Optimized resources (hard macros) Multipliers Memory System-on-chip building blocks FPGA Introduction

6. Basic FPGA Architectural Components

7. Computational Fabric - LUT

8. Computational Fabric - LUT

9. Computational Fabric - LUT

10. Computational Fabric - LUT

11. Computational Fabric - LUT

12. LUTs are fine for implementing any arbitrary combinational logic (output is ONLY a function of its inputs) function. But what about sequential logic (output is a function of input AND previous state information)? Computational Fabric - DFF

13. Computational Fabric - DFF

14. Computational Fabric - DFF

15. Need a mechanism to move results of computation around. Communication: Interconnect & Routing

16. Need a mechanism to move results of computation around. Communication: Interconnect & Routing

17. Need a mechanism to move results of computation around. Communication: Interconnect & Routing

18. LUTs + DFFs can implement any arbitrary digital logic. But not optimally (ASICs give make much better use of silicon area for Power, Speed, routing resources) Arithmetic (Multiply) On chip memory System on chip building blocks Processor, PCI-express, Gigabit Ethernet, ADC, etc. Optimized Resources: Dedicated Logic

19. Optimized Resources: Dedicated Logic

20. Optimized Resources: Dedicated Logic

21. Optimized Resources: Dedicated Logic

22. Optimized Resources: Dedicated Logic

23. Optimized Resources: Dedicated Logic

24. See System Generator User Guide page 71. Next week show example of how to integreate an System Generator core into a FPGA “base” design. System Generator IP core integration

25. Groups of three Continue Implementing Sobel edge detection application, or Create your own IP core to integrate on to an FPGA system In class next week Each group presents 5-6 (less than 10) slides on what they developed, discovered, explored during the week. Xilinx ISE introduction, base system to help integrate your System Generator IP core Back to Linux Assignment