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FPGAs for HIL and Engine Simulation

FPGAs for HIL and Engine Simulation. Field-Programmable Gate Array (FPGA). Memory Blocks. I/O Blocks. Directly access digital and analog I/O. Store data sets or values in user defined RAM. Configurable Logic Blocks (CLBs). Programmable Interconnects.

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FPGAs for HIL and Engine Simulation

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  1. FPGAs for HIL and Engine Simulation

  2. Field-Programmable Gate Array (FPGA) Memory Blocks I/O Blocks Directly access digital and analog I/O Store data sets or values in user defined RAM Configurable Logic Blocks (CLBs) Programmable Interconnects Implement logic using flip-flops and LUTs Route signals through the FPGA matrix Multipliers and DSPs Implement signal processing using multiplier and multiplier-accumulate circuitry

  3. FPGAs - Why Are They Useful? • Hard determinism – Realistic simulation timing, local intelligence • Off-load processing – Achieve real-time performance with more complex simulations • Custom Hardware – Create custom H/W instruments • Reconfigurable hardware personalities – Adapt to multiple UUT types and changing UUT interfaces • Industry standard technology – Off the shelf chips used for specific applications get COTS benefits like Moore’s Law

  4. FPGAs in HIL Test Systems IO UUT µP Signal Conditioning Test Application

  5. FPGAs in HIL Test Systems µP IO UUT FPGA Signal Conditioning Test Application FPGA Personality

  6. FPGAs in HIL Test Systems µP IO UUT NI Reconfigurable I/O (RIO) Platform FPGA Signal Conditioning Test Application FPGA Personality Test Application Interfaces Hardware I/O Interfaces

  7. Mechanical Systems – Engine Sensor Simulation µP FPGA (Engine Simulation) I/O UUT Crank RPMs

  8. Free Engine Simulation Toolkit • Fully featured for Engine Control Unit (ECU) testing • FPGA-based sensor simulation and measurement for ultra-fast pin-to-pin response time & lifetime upgradability • Seamless integration with NI FPGA hardware and NI VeriStand • Scalable design for simple to complex ECU testing • Suitable for open loop or closed loop • Open source architecture customizable with LabVIEW FPGA • Supports any NI FPGA device • Deploy with NI VeriStand 2013 or later • Design with LabVIEW 2013 or later

  9. Engine Simulation Toolkit Building Blocks CPU FPGA ECU Event Waveform Capture Angle Processing Unit (APU) Digital Pattern Generation (i.e. Hall) ECU Event Waveform Capture Digital Pattern Generation ECU Event Waveform Capture Digital Pattern Generation Directional Sensor Simulation Analog Replay (i.e. VR) Directional Sensor Simulation Analog Data Replay Directional Sensor Simulation Analog Data Replay Knock Sensor Simulation ECU Event Timing Capture (Inject & Ignite) Knock Sensor Simulation ECU Event Timing Capture Knock Sensor Simulation ECU Event Timing Capture Speed, Crank Angle, Cycle Angle

  10. Engine Simulation Toolkit Roadmap

  11. Engine Simulation Toolkit Roadmap

  12. Engine Simulation Toolkit Roadmap

  13. Space and performance comparison

  14. Reconfigurable I/O Interfaces V6 ECU µP FPGA I/O V8 ECU Multiple UUT types Evolution of UUT interface

  15. NI VeriStand System Explorer

  16. Analog Replay

  17. Analog Replay Configuration

  18. Analog Replay: Voltage Scaling Configuration

  19. Example FPGA: APU + 1 Analog Replay APU Load Look Up Table Play Look Up Table

  20. Example FPGA : APU + 2 Analog Replay

  21. Digital Pattern Generation

  22. Digital Pattern Generation of Two Cams and a Crank

  23. Digital Pattern Generation Design

  24. Digital Pattern Generation supports complex patterns easily

  25. Example FPGA: 2 Digital Pattern Generations

  26. Knock Sensor Simulation

  27. Knock Sensor Simulation Configuration

  28. Example FPGA: Knock Sensor Simulation Loop

  29. Knock Sensor with 4 Cylinders (Probably had been set to 100% with 4 different amplitudes)

  30. Directional Speed Sensor Simulation

  31. Directional Speed Sensor • Generates pulses of different widths, depending on forward (Tf) or reverse (Tr) rotation, when passing tooth centers • Pulse slightly delayed from center by variable microseconds (Td) Directional sensor: forward Directional sensor: reverse Crank

  32. Directional Speed Sensor

  33. Example FPGA: 1 Directional Speed Sensor Load Tooth Centers Look Up Table From APU

  34. ECU Event Capture

  35. Example FPGA : Typical MPI Injection Measurement (1 x Cylinder) • Event measurement block outputs: • Stuck active (Boolean) • Window all active (Boolean) • Window orphan start edge (Boolean) • Window orphan end edge (Boolean) Digital Input • Event measurement block settings: • Angle Max (degrees) • Angle Min (degrees) • Active High (Boolean) • Time based ‘stuck active’ timeout (milliseconds) • Event capture block outputs: • Event Present (Boolean) • Start Angle (degrees) • End Angle (degrees) • Duration (milliseconds)

  36. Example FPGA : Typical GDI or Diesel Injection Measurement (1 x Cylinder)

  37. Example FPGA : Typical GDI or Diesel Injection Measurement (2 x Cylinder)

  38. Example FPGA : Customize Windowing Per Event

  39. ECU Event Capture Configuration

  40. ECU Event Capture Configuration

  41. Generation and measurement of two events neither wrapping 0 and window does not wrap 0

  42. Generation of one event wrapping zero and one not wrapping zero; window wraps zero and measures both

  43. Start of a full cycle event within window, causing an orphan start edge and a stuck active flag

  44. End of full cycle event within next window, causing an orphan end edge

  45. Future* FPGA : Typical GDI or Diesel Injection Timing & Waveform Measurement Timing Measurement and Capture Analog Input Thresholding Waveform capture *Q4 2014

  46. Case Study Application Creatinga flexible HIL test system with I/O interfaces that require custom timing and synchronization schemes not easily implementable with traditional hardware. NI Products LabVIEW FPGA Module, PXI, and Reconfigurable I/O (RIO) hardware "With LabVIEW FPGA and RIO hardware we were able to quickly and efficiently design custom analog and digital interfaces for our HIL test system.” – Roy Kranz, Wineman Technology Inc. Key Benefit Gaining the ability to efficiently create custom hardware interfaces that can be reconfigured after deployment to adapt to different ECU types and changes to ECU interfaces.

  47. Summary • FPGA-based I/O interfaces are used to expand the capabilities and performance of HIL test systems. • Hard determinism – Realistic simulation timing and local intelligence with 25 ns resolution • Off-load processing – Achieve real-time performance with more complex simulations • Custom Hardware – Create custom H/W instruments • Industry standard technology – Off the shelf chips used for specific applications get COTS benefits • Reconfigurable hardware personalities – Test multiple UUT types and adapt to changes in UUT interfaces without changing hardware

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