Binary Counters

1 / 19

# Binary Counters - PowerPoint PPT Presentation

Binary Counters. Lecture L8.3 Section 8.2. Counters. 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter. State Q2 Q1 Q0 Q2.D Q1.D Q0.D. D . Q . Q0.D. Q0. CLK . !Q. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.

## PowerPoint Slideshow about 'Binary Counters' - issac

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

### Binary Counters

Lecture L8.3

Section 8.2

Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

D

Q

Q0.D

Q0

CLK

!Q

s0 0 0 0 0 0 1

s1 0 0 1 0 1 0

s2 0 1 0 0 1 1

s3 0 1 1 1 0 0

s4 1 0 0 1 0 1

s5 1 0 1 1 1 0

s6 1 1 0 1 1 1

s7 1 1 1 0 0 0

D

Q

Q1.D

Q1

CLK

!Q

D

Q

Q2.D

Q2

CLK

!Q

Divide-by-8 Counter

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 0 0 1

s1 0 0 1 0 1 0

s2 0 1 0 0 1 1

s3 0 1 1 1 0 0

s4 1 0 0 1 0 1

s5 1 0 1 1 1 0

s6 1 1 0 1 1 1

s7 1 1 1 0 0 0

Divide-by-8 Counter

Q1 Q0

00

01

11

10

Q2

1

0

1

1

1

1

Q2.D

Q2.D = !Q2 & Q1 & Q0

# Q2 & !Q1

# Q2 & !Q0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 0 0 1

s1 0 0 1 0 1 0

s2 0 1 0 0 1 1

s3 0 1 1 1 0 0

s4 1 0 0 1 0 1

s5 1 0 1 1 1 0

s6 1 1 0 1 1 1

s7 1 1 1 0 0 0

Divide-by-8 Counter

Q1 Q0

00

01

11

10

Q2

1

1

0

1

1

1

Q1.D

Q1.D = !Q1 & Q0

# Q1 & !Q0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 0 0 1

s1 0 0 1 0 1 0

s2 0 1 0 0 1 1

s3 0 1 1 1 0 0

s4 1 0 0 1 0 1

s5 1 0 1 1 1 0

s6 1 1 0 1 1 1

s7 1 1 1 0 0 0

Divide-by-8 Counter

Q1 Q0

00

01

11

10

Q2

1

1

0

1

1

1

Q0.D

Q0.D = ! Q0

div8cnt.abl

MODULE div8cnt

TITLE 'Divide by 8 Counter'

DECLARATIONS

hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]);

d7R FUNCTIONAL_BLOCK hex7seg;

" INPUT PINS "

CLK PIN 12; " 1 Hz clock (jumper)

clear PIN 11; " switch 1

" OUTPUT PINS "

Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16

Q = [Q2..Q0]; " 3-bit output vector

[a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com';

" Rightmost (units) 7-segment LED display

EQUATIONS

Q.AR = clear;

Q.C = CLK;

Q2.D = !Q2 & Q1 & Q0

# Q2 & !Q1

# Q2 & !Q0;

Q1.D = !Q1 & Q0 # Q1 & !Q0;

Q0.D = !Q0;

[a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g];

d7R.[D2..D0] = Q;

d7R.D3 = 0;

Async clear

div8cnt.abl (cont’d)

Clock

div8cnt.abl (cont’d)

test_vectors(CLK -> Q)

.C. -> 1;

.C. -> 2;

.C. -> 3;

.C. -> 4;

.C. -> 5;

.C. -> 6;

.C. -> 7;

.C. -> 0;

.C. -> 1;

.C. -> 2;

.C. -> 3;

.C. -> 4;

END

Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

D

Q

Q0.D

Q0

CLK

!Q

s0 0 0 0 1 1 1

s1 0 0 1 0 0 0

s2 0 1 0 0 0 1

s3 0 1 1 0 1 0

s4 1 0 0 0 1 1

s5 1 0 1 1 0 0

s6 1 1 0 1 0 1

s7 1 1 1 1 1 0

D

Q

Q1.D

Q1

CLK

!Q

D

Q

Q2.D

Q2

CLK

!Q

3-Bit Down Counter

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 1 1 1

s1 0 0 1 0 0 0

s2 0 1 0 0 0 1

s3 0 1 1 0 1 0

s4 1 0 0 0 1 1

s5 1 0 1 1 0 0

s6 1 1 0 1 0 1

s7 1 1 1 1 1 0

3-Bit Down Counter

Q1 Q0

00

01

11

10

Q2

1

0

1

1

1

1

Q2.D

Q2.D = !Q2 & !Q1 & !Q0

# Q2 & Q1

# Q2 & Q0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 1 1 1

s1 0 0 1 0 0 0

s2 0 1 0 0 0 1

s3 0 1 1 0 1 0

s4 1 0 0 0 1 1

s5 1 0 1 1 0 0

s6 1 1 0 1 0 1

s7 1 1 1 1 1 0

3-Bit Down Counter

Q1 Q0

00

01

11

10

Q2

1

1

0

1

1

1

Q1.D

Q1.D = !Q1 & !Q0

# Q1 & Q0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

s0 0 0 0 1 1 1

s1 0 0 1 0 0 0

s2 0 1 0 0 0 1

s3 0 1 1 0 1 0

s4 1 0 0 0 1 1

s5 1 0 1 1 0 0

s6 1 1 0 1 0 1

s7 1 1 1 1 1 0

3-Bit Down Counter

Q1 Q0

00

01

11

10

Q2

1

1

0

1

1

1

Q0.D

Q0.D = ! Q0

Counters
• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

Up-Down Counter

Up-Down

Counter

clock

Q0

Q1

Q2

UD

UD = 0: count up

UD = 1: count down

Up-Down Counter

UD Q2 Q1 Q0 Q2.D Q1.D Q0.D

UD Q2 Q1 Q0 Q2.D Q1.D Q0.D

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 0 1 1

0 0 1 1 1 0 0

0 1 0 0 1 0 1

0 1 0 1 1 1 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 0 1 1

1 1 0 1 1 0 0

1 1 1 0 1 0 1

1 1 1 1 1 1 0

Up-Counter

Down-Counter

Up-Down Counter

Q1 Q0

00

01

11

10

UD Q2

00

01

11

10

Make Karnaugh maps for Q2.D, Q1.D, and Q0.D