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Counters

Counters. Discussion D5.3 Example 33. Counters. 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter. 3-Bit, Divide-by-8 Counter. Present state Next state. State q2 q1 q0 D2 D1 D0. s0 0 0 0 0 0 1

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Counters

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  1. Counters Discussion D5.3 Example 33

  2. Counters • 3-Bit, Divide-by-8 Counter • 3-Bit Behavioral Counter in Verilog • Modulo-5 Counter • An N-Bit Counter

  3. 3-Bit, Divide-by-8 Counter

  4. Present state Next state State q2 q1 q0 D2 D1 D0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 Divide-by-8 Counter

  5. Present state Next state State q2 q1 q0 D2 D1 D0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 Divide-by-8 Counter q1 q0 00 01 11 10 q2 1 0 1 1 1 1 D2 D2 = ~q2 & q1 & q0 | q2 & ~q1 | q2 & ~q0

  6. Present state Next state State q2 q1 q0 D2 D1 D0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 Divide-by-8 Counter q1 q0 00 01 11 10 q2 1 1 0 1 1 1 D1 D1 = ~q1 & q0 | q1 & ~q0

  7. Present state Next state State q2 q1 q0 D2 D1 D0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 Divide-by-8 Counter q1 q0 00 01 11 10 q2 1 1 0 1 1 1 D0 D0 = ~q0

  8. Divide-by-8 Counter A Divide by 8 counter circuit using D Flip-flops

  9. -- Example 33a: 3-bit divide-by-8 counter library IEEE; use IEEE.STD_LOGIC_1164.all; entity count3a is port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0) ); end count3a;

  10. architecture count3a of count3a is signal D, qs: STD_LOGIC_VECTOR(2 downto 0); begin D(2) <= (not qs(2) and qs(1) and qs(0)) or (qs(2) andnot qs(1)) or (qs(2) andnot qs(0)); D(1) <= (not qs(1) and qs(0)) or (qs(1) andnot qs(0)); D(0) <= not qs(0); -- Three D flip-flops process(clk, clr) begin if clr = '1' then qs <= "000"; elsif clk'event and clk = '1' then qs <= D; end if; end process; q <= qs; end count3a;

  11. count3a Simulation

  12. Counters • 3-Bit, Divide-by-8 Counter • 3-Bit Behavioral Counter in VHDL • Modulo-5 Counter • An N-Bit Counter

  13. count3 clr q(2 downto 0) clk 3-Bit Counter signal count: STD_LOGIC_VECTOR (2 downto 0); Behavior if clr = '1' then count <= "000"; elsif rising_edge(clk) then count <= count + 1; end if; Q <= count;

  14. count3.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity count3b is port( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0) ); end count3b; architecture count3b of count3b is signal count: STD_LOGIC_VECTOR(2 downto 0); begin process(clr,clk) begin if clr = '1' then count <= "000"; elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end count3b; Need signal because q can not be read Asynchronous clear Signal count increments on rising edge of clk

  15. count3 Simulation

  16. Clock Divider mclk = 50 MHz master clock (FPGA Pin T9) signal clk, cclk: std_logic; signal clkdiv: std_logic_vector(23 downto 0); begin -- Divide the master clock (50Mhz) down to a lower frequency. -- clock divider process(mclk, clr) begin if clr = '1' then clkdiv <= X"000000"; elsif mclk'event and mclk = '1' then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); -- mclk/2 = 25 MHz cclk <= clkdiv(17); -- mclk/218 = 190 Hz

  17. Counters • 3-Bit, Divide-by-8 Counter • 3-Bit Behavioral Counter in Verilog • Modulo-5 Counter • An N-Bit Counter

  18. -- Example 33c: modulo-5 counter library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity mod5cnt is port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0) ); end mod5cnt; architecture mod5cnt of mod5cnt is signal count: STD_LOGIC_VECTOR(2 downto 0); begin -- modul0-5 counter process(clk, clr) begin if clr = '1' then count <= "000"; elsif clk'event and clk = '1' then if count = "100" then count <= "000"; else count <= count + 1; end if; end if; end process; q <= count; end mod5cnt;

  19. mod5cnt Simulation

  20. Counters • 3-Bit, Divide-by-8 Counter • 3-Bit Behavioral Counter in Verilog • Modulo-5 Counter • An N-Bit Counter

  21. -- Example 33d: N-bit counter library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter is generic(N : integer := 8); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter;

  22. architecture counter of counter is signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin -- N-bit counter process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end counter; cnt16: counter genericmap(N => 16) port map( clr => clr, clk => clk, q => q );

  23. counter Simulation N = 8

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