COUNTERS

1. COUNTERS Counters Transition Tables Moore Outputs Counter Timing ECEn 224

2. D Q D Q CurrentState StateMemory NextState InputFormingLogic General Sequential Systems ECEn 224

3. D Q D Q A Sequential Counter 2 CurrentState StateMemory +1 Clock edges… NextState The current stateloads the nextstate values inresponse to the clock edge. IFL reacts after some gate delaysto produce a newnext state. Slave Slave Slave Slave CLK Master Master Master Master Master CurrentState 00 01 10 11 00 NextState 01 10 11 00 01 ECEn 224

4. Transition Table for 2-Bit Counter It is the truth table for the input forming logic… It describes what the next state values are as a function of the current state (clock is assumed) ECEn 224

5. D Q D Q N1 Q1 CLK Q0 N0 CLK Implementation of 2-Bit Counter N0 = Q0’ N1 =Q1 Q0 ECEn 224

6. D Q D Q N1 Q1 CLK Q0 N0 CLK Example 2 – A Gray Code Counter N1= Q0 N0 = Q1’ ECEn 224

7. Example 3 – Not All Count Values Used Desired count sequence = 00 – 01 – 11 - 00 … What should next state for 10 be? ECEn 224

8. N1 = Q0•Q1’ N0 = Q0’ Example 3 – Not All Count Values Used Do the normal K-map minimization with don’t cares ECEn 224

9. Example 4 – A Ring Counter Desired count sequence = 001 – 010 – 100 - 001 … ECEn 224

10. Example 4 – A Ring Counter Desired count sequence = 001 – 010 – 100 - 001 … N2 N1 N0 Doing KMaps leads to: N2 = Q1 N1 = Q0 N0 = Q2 ECEn 224

11. D Q D Q D Q Example 4 – A Ring Counter Q2 Q1 Q0 CLK ECEn 224

12. Initial State • When a sequential circuit is powered on, we have no guarantee it will start in any particular state • We must make sure our counters don’t start in an invalid state • They could remain stuck in invalid states! • Most digital systems have a reset signal that is asserted after power up • Designers must use flip flops with reset/set inputs as needed to achieve desired startup behavior ECEn 224 13 COUNTERS Page 12

13. A Ring Counter with Reset D Q SET D Q RST D Q RST Q2 Reset causes circuit to start in state “001” Q1 Q0 RESET CLK ECEn 224 13 COUNTERS Page 13

14. General Counter Design Procedure • Write transition table for counter • Use X’s as appropriate • Reduce each NX variable to a minimized equation • Implement input forming logic (IFL) using gates • Draw schematic using FF’s + IFL ECEn 224

15. T Q T Q T Q Counters With Alternative FF’s CurrentState StateMemory InputFormingLogic T Inputs ECEn 224

16. Excitation Table for T Flip Flop Transition Table Excitation Table Rearranging rows and/or columns… Tells how inputs affect output Tells what input is needed to achieve desiredoutput transition In the end, they are the same table, just rearranged… ECEn 224

17. TFF Counter Design Using Augmented Transition Table Next state values Inputs to apply to achieve desired next state ECEn 224

18. TFF Counter Design Using Augmented Transition Table T2 T2 = Q1•Q0T1 = Q0T0 = ‘1’ Next state values Inputs to apply to achieve desired next state ECEn 224

19. T Q T Q T Q TFF Counter Design Q2 CLK Q1 CLK ‘1’ Q0 CLK ECEn 224

20. Excitation Table for JK Flip Flop Rearranging rows and/or columns… Tells what inputs to applyto achieve desiredoutput transition Do you see why the X’s? Tells how inputs affect output In the end, they are the same table, just rearranged… ECEn 224

21. JKFF Gray Code Counter Design Next state values Inputs to apply to achieve desired next state ECEn 224

22. JKFF Gray Code Counter Design J2 = Q1•Q0’K2 = Q1’•Q0’ J1 = Q2’•Q0K1 = Q2•Q0 J0 = Q2•Q1 + Q2’•Q1’ = K0’K0 = Q2’•Q1 + Q2•Q1’ = Q2  Q1 Next state values Inputs to apply to achieve desired next state ECEn 224

23. General Counter Design Procedure • Write transition table for counter • Use X’s as appropriate • If not DFF’s, augment table • Reduce each FF input variable to a minimized equation • Implement IFL with gates • Draw schematic using FF’s + IFL ECEn 224

24. D Q D Q CurrentState StateMemory NextState InputFormingLogic OutputFormingLogic Outputs Counters With Outputs Outputs = f (CurrentState) ECEn 224

25. Counters With Outputs Z=1 when count={0,3,6} Z is called a Moore or static output. It is a function only of the current state. ECEn 224

26. Combined Transition Table Current state Next state Output Z = Q2’•Q1’•Q0’ + Q2’•Q1•Q0 + Q2•Q1•Q0’ (implement OFL with gates) ECEn 224

27. D Q D Q Counter With A Moore Output D Q N2 Q2 CLK N1 Z Q1 CLK N0 Q0 OFL IFL CLK ECEn 224

28. D Q D Q N1 Q1 CLK Q0 N0 CLK Counter Timing Characteristics tsetup tIFL tCLK-Q CLK CurrentState (Q’s) 00 01 10 Next State(N’s) 01 10 TClockPeriod TClockPeriod >= tCLK-Q + tIFL + tsetup ECEn 224

29. Counter Timing Example • tCLKQ = 1ns • tIFL = 7ns • tsetup = 2ns • Recall the following: • T = Clock period • f = Clock frequency or rate • T = 1/f • f = 1/T • T >= 1ns + 7ns + 2ns = 10 ns (10 x 10-9 s) • f <= 1/T = 100 MHz (100 x 106 Hz) ECEn 224

30. Output Timings tOFL tOFL tCLKQ tCLKQ Moore outputs appear tCLKQ + tOFLafter the clock edge. CLK CurrentState 010 011 100 Z ECEn 224

31. Counters and Timing • The count sequence affects the size of IFL • The size of the IFL affects tIFL • tIFL affects TClockPeriod • Choosing binary counts is not always fastest or smallest ECEn 224

32. Example Problem • Design a 3-bit binary counter • The Z output is TRUE iff count value is even • The Y output is TRUE iff count value is multiple of 3 ECEn 224