PiezoMEMS Foundry

1. PiezoMEMS Foundry Naomi Montross, Joe Evans, Gerald Salazar, Spencer Smith, Bob Howard, Radiant Technologies, Inc. 2019 International Workshop on Acoustic Transduction Materials and Devices May 7, 2018

2. Radiant Technologies has completed the first test wafer of its I-Beam piezoMEMS process. Radiant will accept capacitor or piezoMEMS foundry projects from universities and organizations to run on this process.

3. Introduction • Objective of the I-Beam Process • Description of the Process • Example Devices • Project Flow • Contact Info

4. Objective of the Foundry Service • Shift the focus from the complexity of piezoMEMS fabrication to more important issues associated with device design and performance . • Reduce the time and cost to complete the fabrication of piezoMEMS or integrated capacitor designs. • Generate higher yield to increase the population of functional devices available in a project. • Provide a path to physically plug piezoMEMS and integrated capacitor circuits directly into analog or digital control circuits.

5. Overview of Process Flow • The three fundamental steps of the process flow: • Fabricate the solid state capacitors atop the wafer. • Deposit the metallic I-Beams above the capacitors and pattern them into the geometry of the final mechanical structures. • Execute a single through-wafer DRIE step to remove all silicon from beneath the I-Beams. • The process utilizes thick metal layers above the actuator and sensor capacitors to create robust structures.

6. Process Flow Start with thin PZT Capacitors • Simple • Repeatable • Robust • Affordable • Fast • High Yield Deposit I-Beam Execute backside DRIE etch

7. From Layout…to Device… Through-wafer hole Cantilever

8. …to Test… Etched backside well seen through transparent PZT/SiO2 layers. Electrodes PZT Thirty second loop of 1m 4/20/80 PNbZT measured with AFM. Calibrated. Error = 1.13m/V x 0.1Vpp = 0.11m

9. …to Package • If the die is 1.7 millimeters on a side or smaller, it will fit in a TO-18 transistor can. • If the die is larger than 1.7mm, Chrome/Copper/Gold solder pads on the die allow soldering directly to printed circuit boards. Radiant uses an SOIC format on a 3.4mm x 3.4mm die floor plan

10. Solid State Module • Exploded view of a Radiant integrated PZT capacitor. MIRROR BE VIA TE VIA ILD M1 PZT Passivation FE Electrodes Thermal Silicon Dioxide Substrate • Patterned BE • FE overlap of BE Edge • Combine PZT/Glass passivation for reliability.

11. Advantages of Radiant’s Capacitor Stack ILD allows non-circuit metal layers to be positioned above the capacitor. ILD Passivation improves reliability and capacitor survivability in post processing. Ferroelectric material overlap of BE edge prevents TDDB arising from etch damage at the ferroelectric boundary. Mirror, I-Beam, Sensor ILD M1 FE Silicon substrate Patterned Bottom Electrode provides more flexible device design.

12. Uniformity & Yield • No shorts out of 64 capacitors across two wafers. • 1m-thick- 100,000m2- 4/20/80 PNbZT - Platinum electrodes

13. Example Device • Membrane with Center Mass Backside

14. Example Device • Dual Strings Backside

15. Example Device • Tuning Fork

16. Example Devices

17. Project Flow • Radiant provides a GDS II file of the STARTW project. STARTW includes the wafer boundaries, alignment marks, and an assortment of design-rule-compliant cells such as vias, capacitors, solder pads, etc. that are building blocks for larger structures. • Customer executes design. • Radiant conducts a final design review of the project, acquires masks and fabricates the wafers. • Finished dice are be submitted to the researcher. • Radiant advises on testing.

18. StartW Wafer 4” Wafer Boundary Alignment Marks Cell Library

19. Contact • Please contact Naomi Montross or Joe Evans at Radiant Technologies in Albuquerque. • +1-505-842-8007 • radiant@ferrodevices.com *** • This PowerPoint file will be on-line at www.FerroFoundry.com