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An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture Shanna-Shaye Forbes*, Hugo A. Andrade**, Hiren D. Patel* and Edward A. Lee*. Shanna-Shaye Forbes sssf@eecs.berkeley.edu *University of California, Berkeley *National Instruments Corporation. Overview.

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An Automated Mapping of Timed Functional Specification to A Precision Timed ArchitectureShanna-Shaye Forbes*, Hugo A. Andrade**, Hiren D. Patel* and Edward A. Lee*

Shanna-Shaye Forbes

sssf@eecs.berkeley.edu

*University of California, Berkeley

*National Instruments Corporation

overview
Overview

Programming languages generally abstract away the notion of timing at the software level. We overcome this shortcoming by combining an architecture which has repeatable timing with a model based programming model with temporal semantics.

pret precision timed machines
PRET:Precision Timed Machines

Related Work

ISA extensions with timing instructions

Multithreaded architecture with scratchpad memories and time-triggered access to main memory

Simulator accepts programs in C with additional timing instructions.

JOP(Vienna), SPEAR(Vienna), KEP(Kiel), REMIC (Auckland)

Forbes, Oct. 27, 2008

labview
LabVIEW

Actor oriented structured data flow programming language G

C software synthesis backend to automatically generate code

Has the ability to incorporate legacy C code into a model based design

labview cont
LabVIEW cont.

Timed loops allow the user to specify the period and offset at which functions are to be executed

An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture, Forbes

timed loop
Timed Loop

Forbes, Oct. 27, 2008

plug in
Plug-in
  • LabVIEW has a plug-in architecture.
  • We implemented a plug-in that maps LabVIEW to the PRET architecture.
  • Implements timed loops with the PRET timing instruction.
simple mutual exclusion example
Simple mutual exclusion example

Producer

Observer

Consumer