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Technology Readiness Levels TRLs

Technology Readiness Levels TRLs. Andrew Faulkner. Purpose. To identify where we are in the long term development cycle of the SKA technology To identify ‘missing’ development work To convince ourselves and the international community that we are ‘on-track’. NASA TRL definitions.

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Technology Readiness Levels TRLs

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  1. Technology Readiness LevelsTRLs Andrew Faulkner

  2. Purpose • To identify where we are in the long term development cycle of the SKA technology • To identify ‘missing’ development work • To convince ourselves and the international community that we are ‘on-track’

  3. NASA TRL definitions

  4. Full System Test & Operations SKA in operation SKA Phase 1 System/Subsystem Development Target for AAVP Technology Demonstration PrepSKA & SKADS Technology Development SKADS Research to Prove Feasibility Mostly pre-SKADS work Basic Technology Research TRLs mapped to SKA timeline Ref: NASAhttp://en.wikipedia.org/wiki/Technology_Readiness_Level

  5. Review undertaken

  6. DS3 TRLs TRL: 1 2 3 4 5 6 7 8 9 DS3-T1Phase Transfer: optical tx terminal equipment Analogue fibre data links COTS Data links Component data links: DFB laser based link subsystems Components for DFB laser subsystems 10 Gbps 1550 nm SMF subsystems Components for 10 Gbps 1550 nm SMF link DS3-T2 Backend Processing Correlator Software architecture DS3-T3 Design of SKACost tool and simulation Conceptual design of SKA Station level beamforming

  7. TRL: 1 2 3 4 5 6 7 8 9 DS4-T1LNAInP Si-Ge Si GaAs ADC InP Si DS4-T2Digitisation require’ts DS4-T3RFI algorithms:Excision Detection Spectral filtering Spatial filtering Single channel filtering DS4-T4 Antenna: Vivaldi non-Vivaldi array configuration Differential LNA + matching DS4-T5 Beamforming:Analogue Photonic Digital algorithms Digital hardware DS4-T6Mechanical Const’n: Array construction Cooling Electronics construction Material choice Analogue sig. cond. RFI Shielding Clock dist’n : Station level Board level

  8. DS5 & 6 TRLs TRL: 1 2 3 4 5 6 7 8 9 DS5-T1Array performance DS5-T2 Low cost manufacturability Tile electronics Digital processing Array material choice DS6 System Clock distribution

  9. Observations • SKADS is where we would expect: TRL 3 – 6 • The lowest TRLs typically require large implementations • There will be some ‘normalising’ of the figures • The relationship of today’s design and SKA is not clear enough But……..

  10. System related TRLs We need to know/show system parameters are met e.g.: • System temperature • Dynamic range performance • Cost! • Beam purity • Polarisation • AAs meet Power requirements • etc This is tricky! Need to convert system level work into technical performance measures

  11. Over this final year of SKADS We will be refining the TRL of System and Components Please keep commenting …..

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