Topics

1. Topics • Latches and flip-flops. • RAMs and ROMs.

2. Register • Stores a value as controlled by clock. • May have load signal, etc. • In CMOS, memory is created by: • capacitance (dynamic); • feedback (static).

3. Variations in registers • Form of required clock signal. • How behavior of data input around clock affects the stored value. • When the stored value is presented to the output. • Whether there is ever a combinational path from input to output.

4. Register terminology • Latch: transparent when internal memory is being set from input. • Flip-flop: not transparent—reading input and changing output are separate events.

5. Clock terminology • Clock edge: rising or falling transition. • Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0).

6. Registerd parameters • Setup time: time before clock during which data input must be stable. • Hold time: time after clock event for which data input must remain stable. clock data

7. Dynamic latch Stores charge on inverter gate capacitance:

8. Latch characteristics • Uses complementary transmission gate to ensure that storage node is always strongly driven. • Latch is transparent when transmission gate is closed. • Storage capacitance comes primarily from inverter gate capacitance.

9. Latch operation •  = 0: transmission gate is off, inverter output is determined by storage node. •  = 1: transmission gate is on, inverter output follows D input. • Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.

10. Stored charge leakage • Stored charge leaks away due to reverse-bias leakage current. • Stored value is good for about 1 ms. • Value must be rewritten to be valid. • If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.

11. Multiplexer dynamic latch

12. Non-dynamic latches • Must use feedback to restore value. • Some latches are static on one phase (pseudo-static)—load on one phase, activate feedback on other phase.

13. Recirculating latch Static on one phase:

14. Edge-triggered flip-flop D Q 

15. Master-slave operation •  = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change. •  = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value.

16. High-density memory architecture

17. Memory operation • Address is divided into row, column. • Row may contain full word or more than one word. • Selected row drives/senses bit lines in columns. • Amplifiers/drivers read/write bit lines.

18. Read-only memory (ROM) • ROM core is organized as NOR gates—pulldown transistors of NOR determine programming. • Mask-programmable ROM uses pulldowns to determine ROM contents.

19. Flash memory • Flash: electrically erasable PROM that can be programmed with standard voltages. • Uses dual capacitor structure. • Available in some digital processes for integrated memory, but raises the price of the manufacturing process.

20. ROM core circuit

21. SRAM critical path core Sense amp

22. Row decoders • Decode row using NORs:

23. Static RAM (SRAM) • Core cell uses six-transistor circuit to store value. • Value is stored symmetrically—both true and complement are stored on cross-coupled transistors. • SRAM retains value as long as power is applied to circuit.

24. SRAM core cell

25. SRAM core operation • Read: • precharge bit and bit’ high; • set select line high from row decoder; • one bit line will be pulled down. • Write: • set bit/bit’ to desired (complementary) values; • set select line high; • drive on bit lines will flip state if necessary.

26. SRAM sense amp

27. Sense amp operation • Differential pair—takes advantage of complementarity of bit lines. • When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm. • Sense amp can be cross-coupled to increase speed.

28. 3-transistor dynamic RAM (DRAM) • First form of DRAM—modern commercial DRAMs use one-transistor cell. • 3-transistor cell can easily be made with a digital process. • Dynamic RAM loses value due to charge leakage—must be refreshed.

29. 3-T DRAM core cell

30. 1-T RAM • 1 transistor + 1 capacitor: word bit

31. 1-T DRAM with trench capacitor

32. 1-T DRAM with stacked capacitor

33. Embedded DRAM • Embedded DRAM is integrated with logic. • DRAM and logic processes are hard to make compatible. • Capacitor requires high temperatures that destroy fine-line transistors. • Embedded DRAM is less dense than commodity DRAM.

34. 3-T DRAM operation • Value is stored on gate capacitance of t1. • Read: • read = 1, write = 0, read_data’ is precharged; • t1 will pull down read_data’ if 1 is stored. • Write: • read = 0, write = 1, write_data = value; • guard transistor writes value onto gate capacitance. • Cannot support full connectivity between all data path elements—must choose number of transfers per cycle allowed. • A bus circuit is a specialized multiplexer circuit. • Two major choices: pseudo-nMOS, precharged.