Test chips for radiation tolerance survey in TSMC 130nm technology

1. Test chipsfor radiation tolerance surveyin TSMC130nmtechnology Stefano Michelis 19/6/2014

2. TSMC 130nm • Since the future with IBM technology is uncertain it is mandatory to find a suitable back-up technology • First immediate candidate is TSMC 130nm technology as we are already using the 65nm node (with good intrinsic radiation tolerance up to 200-300Mrad). • It is necessary to characterize the new technology with TID, displacement damage and SEU. • For this purpose several test structures have been designed and submitted

3. TSMC 130nm fabs • TSMC has three fabs for the 130nm: • Fab14 in 12 inches wafers with 6 submission/year • Fab6 in 8 inches wafers with only 2 submissions/year • Fab12 in 12 inches wafers with 4 submission/year • The radiation effects may change with different fabs • In our community we mainly need 8 inches wafers for production but we cannot have only 2 submissions/year • We hope that the 8 inches and 12 inches processes will not differ much in term of radiation tolerance. If this is the case, prototyping can be done in 12 inches and production in 8 inches. • Therefore 2 fabs will be characterized (Fab14 and Fab6) • The first submission (18th June) is in the 12 inches • Next submission in 8 inches will be in September 2014. The same basic test-structure will be submitted.

4. CERN submission on 4thJune: RADTEST1 We need to fill 25mm2 (min area) Noise chip 2060x2060 um2 TID_chip 2060x2060 um2 TID_chip 2060x2060 um2 The total area is 26 mm2 We will get around 100 Noise chips 100 Digital chips 400 TID_chips Digital chip 2060x2060 um2 TID_chip 2060x2060 um2 TID_chip 2060x2060 um2 Thanks to colleagues in Cracow for their big help (Mirek, Marek and Tomek)

5. Noise chip Designed completely in Cracow for transistor noise measurement Following Jan Kaplon recommendation

6. Digital chip PLL Shift Register HD library Llopart • The digital chip contains • 2 shift registers for SEU • 1 PLL designed in Cracow with SLVS pads • 3 ring oscillators for TID tests RO TSMC lib RO CK TSMC lib Shift Register TSMC CK library RO HD Llopart lib

7. Different libraries • TSMC std lib is composed by unbalanced Pmosand NMOS: for the smaller Inverter • Nmos=430n/130n • Pmos=635n/130n • TSMC Ck lib is composed by balanced logic • Nmos=450n/130n • Pmos=1270n/130n • Llopart lib is High Density • Nmos=130n/130n • Pmos=650n/130n

8. Oscillating frequency • TSMC Ring Oscillator:2.475MHz • Nominal average current 165uA • TSMC CK Ring Oscillator:3.095MHz • Nominal average current 109uA • Llopart HD Ring Oscillator: 2.097MHZ • Nominal average current 70uA

9. TID chip Design to test single device (transistors, diodes, resistor) with TID. We will use our test facility with X-ray machine and probe station.

10. TID_subchip_NMOS_core_1 TID_subchip_PMOS_core_2 TID_subchip_IO_3 TID_subchip_4_Opamp TID_subchip_NMOS_core_5 TID_subchip_PMOS_core_6 TID_subchip_BGP_7 There are 7 subchips. Each subchip is composed by two rows of 16 pads each, for a total of 32 terminals

11. Pinout Core NMOS Core PMOS +diodes I/O FOXFET Resistances Opamps Single gate core NMOS Single gate core PMOS

12. Analog blocks 2 Opamps are in the test structures to test the radiation effects on basic analog blocks: • N-input: Phase Margin=94degree, GBW=322KHz • P-input: Phase Margin=74degree, GBW=825KHz A Bandgap with DTNMOS have been also laid-out. Since we don’t know the radiation tolerance of the technology I preferred to design all the NMOS with Enclosed Layout (ELT)

13. Bandgap = gate1 R gate2 R gate3

14. BGP resistance selection

15. Conclusions • TSMC 130 nm technology is under investigation for finding a candidate back-up technology for future LHC experiment upgrades • Different tests structures have been already submitted to check the radiation tolerance (TID, DD and SEU) • We need to survey 2 fabs (12 and 8 inches) as our community is prepared to handle 8 inches wafers, but for this option there are only 2 submissions/year • First tests foreseen for end-august, september