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  1. Multicore Processors (3) Dezső Sima Spring 2008 (Ver. 2.1)  Dezső Sima, 2008

  2. 10.1.3 Dual/quad-core server processors Dual-Core Xeon UP-lines Dual/Quad-Core Xeon DP-lines Dual-Core Xeon MP-lines

  3. 10.1.3 Dual/quad-core server processors Dual-Core Xeon UP-lines • Xeon 3000 - line Core 2 Duo 60 nm 9/2006 (Core based, monolithic, dual-core)

  4. Xeon 3000 line (1) 10.1.3 Xeon 3000 UP-line (Conroe) Table: Main features of the dual-core Xeon 3000 UP-line [1.8], [1.9]

  5. 10.1.3 Dual/quad-core server processors Dual/Quad-Core Xeon DP-lines • Xeon DP 2.8 Paxville DP 90 nm 10/2005 (Netburst based, multi-chip, two Irwindale cores) Dempsey 65 nm • Xeon 5000 line 5/2006 (Netburst based, multi-chip, two Cedar Mill cores) • Xeon 5100 line Woodcrest 65 nm 6/2006 (Core based, monolithic, dual-core) Clovertown 65 nm • Xeon 5300 line 11/2006 (Core based, multi-chip, two Woodcrest chips)

  6. 10.1.3 Xeon DP 2.8 (Paxville DP) (1) Intel’s first 64-bit Xeon Paxville Nocona Nocona Irwindale (2 x Irwindale cores) (L2 enlarged to 2MB) (DP enhanced Prescott) (DP enhanced Prescott 2M) 6/2004 10/2004 90 nm 112 mm2 125 mtrs Xeon DP 2.8 – 3.4 Xeon DP 2.8J - 3.4J mPGA 604 2/2005 9/2005 90 nm 135 mm2 169 mtrs Xeon DP 2.8 – 3.6 Xeon DP 3.8 mPGA 604 10/2005 11/2005 90 nm 2 x 135 mm2 2 x 169 mtrs Xeon DP 2.8 Xeon MP 7020-7041 mPGA 604 In contrast: corresponding desktop processors have the LGA 775 socket. Figure: Genealogy of the Xeon Paxville core Sources: http://www.theinquirer.net/default.aspx?article=16879 http://www.gamepc.com/labs/view_content.asp?id=x36o252&page=2 http://www.xbitlabs.com/articles/cpu/display/opteron-xeon-workstation_5.html

  7. 10.1.3 Xeon DP 2.8 (Paxville DP) (2) Heat Sink Die Die size capacitors FC-mPGA4 package Package pin Pin side capacitors The FC-mPGA package interfaces with the motherboard via an mPGA604 socket Figure: Packaging of the Paxville processor Source: - „Dual-Core Intel Xeon Processor 2.80 GHz Datasheet,” Oct. 2005, http://download.intel.com/design/Xeon/datashts/30915801.pdf

  8. 10.1.3 Xeon DP 2.8 (Paxville DP) (3) Figure Connecting the two Irwindale cores in the large Paxville Package (?) [1.3]

  9. 10.1.3 Xeon DP 2.8 (Paxville DP) (4) Figure: Packaging of the Paxville (two Irwindale dies are mounted on a carrier and the carrier is packaged as a 604 package” Source: Conolly C., „Intel Paxville Dual Core Xeon and the ASsus PVL-D Intel 7520,” Oct. 2005, http://www.gamepc.com/labs/view_content.asp?id=paxville&page=1

  10. 10.1.3 Xeon DP 2.8 (Paxville DP) (5) Series (Paxville DP) Dual/Quad-Core DC Models Xeon DP 2.8 Microarchitecture Netburst Cores 2*Irwindale dies Intro. 10/2005 Technology 90 nm Die size 2*135 mm2 Nr. of transistors 2*169 mtrs fc [GHz] 2.8 L2 2*2 MB FSB [MT/s] 800 TDP [W] 135 Socket PGA 604 EM64T HT ED VT EIST La Grande AMT2 Table: Dual-Core Xeon DP-lines (1) [1.8], [1.9]

  11. 10.1.3 Xeon 5000 DP-line (Dempsey) (1) Figure: Block diagram of the Dempsey (Cedar Mill-based) Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf

  12. 10.1.3 Xeon 5000 DP-line (Dempsey) (2) Figure: Packaging of the Dempsey http://www.tecchannel.de/_misc/img/detail1000.cfm?pk=342850&fk=432919&id=il-74145482909021379

  13. 10.1.3 Xeon 5000 DP-line (Dempsey) (3) Figure: The Xeon DP Dempsy with the two FB-DIMM capable Blackford chipset [1.2]

  14. 10.1.3 Xeon 5000 DP-line (Dempsey) (4) Series (Paxville DP) 5000(Dempsey) Dual/Quad-Core DC DC Models Xeon DP 2.8 5030-5080 Microarchitekture Netburst Netburst Cores 2*Irwindale dies 2*Cedar Mill dies Intro. 10/2005 5/2006 Technology 90 nm 65 nm Die size 2*135 mm2 2*81 mm2 Nr. of transistors 2*169 mtrs 2*188 mtrs fc [GHz] 2.8 2.6-3.73 L2 2*2 MB 2*2 MB FSB [MT/s] 800 667/1066 TDP [W] 135 95/130 Socket PGA 604 LGA 771 EM64T HT ED VT EIST La Grande AMT2 Table: Dual-Core Xeon DP-lines (2) [1.8], [1.9]

  15. 10.1.2 Xeon 5100 DP-line (Woodcrest) (1) Figure: Block diagram of the Merom, Conroe and Woodcrest processors Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf

  16. 10.1.3 Xeon 5100 DP-line (Woodcrest) (2) Woodcrest Figure: Die shot of the Woodcrest (5100 series) processor (L2: 4 MB) Source: http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg

  17. 10.1.3 Xeon 5100 DP-line (Woodcrest) (3) Merom Woodcrest Conroe Figure: Contrasting the die shots of Merom, Conroe and Woodcrest Sources: Kubicki K., „Intel 2006 Mobile CPU Roadmap Update,” Mai 2006, http://www.dailytech.com/Article.aspx?newsid=2546 Hübner, T., „Intel Core 2 Duo E6700 und E6600,” July 2006, http://www.computerbase.de/artikel/hardware/prozessoren/2006/test_intel_core_2_duo_e6700_e6600/1/ http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg

  18. 10.1.3 Xeon 5100 DP-line (Woodcrest) (4) Series (Paxville DP) 5000(Dempsey) 5100(Woodcrest) Dual/Quad-Core DC DC DC Models Xeon DP 2.8 5030-5080 5110-5160 Microarchitekture Netburst Netburst Core Cores 2*Irwindale dies 2*Cedar dies Single dies Intro. 10/2005 5/2006 6/2006 Technology 90 nm 65 nm 65 nm Die size 2*135 mm2 2*81 mm2 143 mm2 Nr. of transistors 2*169 mtrs 2*188 mtrs 291 mtrs fc [GHz] 2.8 2.6-3.73 1.6-3.0 L2 2*2 MB 2*2 MB 4 MB FSB [MT/s] 800 667/1066 1066/1333 TDP [W] 135 95/130 65/80 Socket PGA 604 LGA 771 LGA 771 EM64T HT ED VT EIST (5140 or above) La Grande AMT2 Table: Dual-Core Xeon DP-lines (3) [1.8], [1.9]

  19. 10.1.3 Xeon 5300 DP-line (Clovertown) (1) Figure: The Xeon 5300 series (Clovertown) dies are built up of two dual core Woodcrest [1.4]

  20. 10.1.3 Xeon 5300 DP-line (Clovertown) (2) Figure: Packaging the Clowertown Source: Wasson S., „Intel’s Woodcrest procdessor previewed,” May 2006, http://techreport.com/etc/2006q2/woodcrest/index.x?pg=2

  21. 10.1.3 Xeon 5300 DP-line (Clovertown) (3) Series (Paxville DP) 5000(Dempsey) 5100(Woodcrest) 5300(Clovertown) Dual/Quad-Core DC DC DC QC Models Xeon DP 2.8 5030-5080 5110-5160 E5310-5345/X5355 Microarchitekture Netburst Netburst Core Core Cores 2*Irwindale dies 2*Cedar dies Single dies 2*Woodcrest dies Intro. 10/2005 5/2006 6/2006 11/2006 Technology 90 nm 65 nm 65 nm 65 nm Die size 2*135 mm2 2*81 mm2 143 mm2 2*143 mm2 Nr. of transistors 2*169 mtrs 2*188 mtrs 291 mtrs 2*291 mtrs fc [GHz] 2.8 2.6-3.73 1.6-3.0 1.6-2.66 L2 2*2 MB 2*2 MB 4 MB 2*4 MB FSB [MT/s] 800 667/1066 1066/1333 1066/1333 TDP [W] 135 95/130 65/80 80/120 Socket PGA 604 LGA 771 LGA 771 LGA 771 EM64T HT ED VT EIST (5140 or above) La Grande AMT2 Table: Dual-Core Xeon DP-lines (4) [1.8], [1.9]

  22. 10.1.3 Dual/quad-core server processors Dual-Core/Quad-Core Xeon MP-lines • Xeon 7000 line Paxville MP DC 90 nm 11/2005 (Netburst based, multi-chip, two Irwindale dies) Tulsa DC 65 nm • Xeon 7100 line 8/2006 (Netburst based, monolithic, Cedar Mill based) Tigerton DC 65 nm • Xeon 7200 line 9/2007 (Core 2 based, multi-chip, two single-core Woodcrest dies) Tigerton QC 65 nm • Xeon 7300 line 9/2007 (Core 2 based, multi-chip, two Woodcrest dies)

  23. Xeon 7000 line (Paxville MP) (1) 10.1.3 Xeon 7000 MP-line (Paxville MP) (1) Series 7000(Paxville MP) Dual/Quad-Core DC Models 7020-7041 Microarchitecture Netburst Cores 2*Irwindale dies Intro. 11/2005 Technology 90 nm Die size 2*135 mm2 Nr. of transistors 2*169 mtrs fc [GHz] 2.66-3.0 L2 2*1/2 MB 1 L3 FSB [MT/s] 667/800 TDP [W] 95/150 Socket PGA604 EM64T HT ED VT EIST La Grande AMT2 1 Concerning the L2 cache size, there is a contradiction in Intel’s documentation; whereas according to the datasheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches. Table: Dual-Core Xeon MP-lines (1) [1.8], [1.9]

  24. 10.1.3 Xeon 7100 MP-line (Tulsa) (1) Figure: Block diagram and die shot of Tulsa [1.5]

  25. 10.1.3 Xeon 7100 MP-line (Tulsa) (2) Figure: Detailed block diagram of Tulsa (Cedar Mill-based) Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf

  26. 10.1.3 Xeon 7100 MP-line (Tulsa) (3) Figure: Die shot of Tulsa (L3: 16 M) Source: Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/

  27. 10.1.3 Xeon 7100 MP-line (Tulsa) (4) Tulsa (435 mm2) Cedar Mill (81 mm2) 2 x 2 MB L2 2 x 1 MB L” + 16 MB L3 Figure: Contrasting the Cedar Mill and Tulsa die shots Sources: Huynh T., „Pressler: Intel Extreme Edition 955,” Dec. 2005, http://www.sudhian.com/index.php?/articles/show/pressler_intel_extreme_edition_955_prescotts_last_hurrah/, Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/

  28. 10.1.3 Xeon 7100 MP-line (Tulsa) (5) Series 7000(Paxville MP) 7100(Tulsa) Dual/Quad-Core DC DC Models 7020-7041 7110M-7140M / 7110N-7150N Microarchitekture Netburst Netburst Cores 2*Irwindale dies Cedar Mill-based single die Intro. 11/2005 8/2006 Technology 90 nm 65 nm Die size 2*135 mm2 435 mm2 Nr. of transistors 2*169 mtrs 1328 mtrs fc [GHz] 2.66-3.0 2.5-3.5 L2 2*1/2 MB 1 2*1 MB L3 4/8/16 MB FSB [MT/s] 667/800 667/800 TDP [W] 95/150 95/150 Socket PGA604 PGA604 EM64T HT ED VT EIST La Grande AMT2 1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the datasheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches. Table: Dual-Core Xeon MP-lines (2) [1.8], [1.9]

  29. 10.1.3 Xeon 7200/7300 MP-lines (Tigerton DC/Tigerton) (1) 512 GB Figure: Intel’s Caneland platform including the QC 7200/7300 (Tigerton) processors and the 7300 (Clarksboro) chipset

  30. 10.1.3 Xeon 7200/7300 MP-lines (Tigerton DC/Tigerton) (2) Series 7000(Paxville MP) 7100(Tulsa) 7300(Tigerton) 7200(Tigerton DC) 2xSC Dual/Quad-Core DC DC 2xDC E7210/E7220 Models 7020-7041 7110M-7140M / 7110N-7150N E7310/E7320/E7330/E7340/X7350 Core 2 Microarchitekture Netburst Netburst Core 2 2×SC Woodcrest dies Cores 2*Irwindale dies Cedar Mill-based single die 2×Woodcrest dies 9/2007 Intro. 11/2005 8/2006 9/2007 65 nm Technology 90 nm 65 nm 65 nm 2*143 mm2 Die size 2*135 mm2 435 mm2 2*143 mm2 2*291 mtrs Nr. of transistors 2*169 mtrs 1328 mtrs 2*291 mtrs 2.4 / 2.93 fc [GHz] 2.66-3.0 2.5-3.5 1.6/2.13/2.4/2.4/2.93 2×4 MB L2 2*1/2 MB 1 2*1 MB 2×2/2×2/2×3/2×4!2×4 MB --- L3 4/8/16 MB --- 1066 FSB [MT/s] 667/800 667/800 1066 80 TDP [W] 95/150 95/150 80/80/80/80/130 Socket PGA604 PGA604 PGA604 PGA604 EM64T HT ED VT EIST La Grande (Except E7310) AMT2 1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the datasheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches. Table: Dual- and Quad-Core Xeon MP-lines (2) [1.8], [1.9]

  31. 10.1.3 Guessed road map of Intel processors (1) Figure 5.7: Future 65 nm processors (Overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered

  32. 10.1.3 Guessed road map of Intel processors (1) Figure 5.8: Future 45 nm processors (overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered

  33. 10.1 Published road map of Intel processors Figure: Roadmap of Intel’s lines Source: Thrax, „ Core 2 Duo and the future of Intel,” Nov. 2006, http://www.short-media.com/review.php?r=343

  34. 10.1.4 Dual/quad-core Itanium processors Dual/quad-core Itanium 2lines • Dual-core Itanium 2 Montecito 90 nm 7/2006 (Itanium 2 based, monolithic) Tukwila 65 nm • Quad-core Itanium 2 2008 (Itanium 2 based, monolithic)

  35. 10.1.4 Dual-core Itanium 2 (Montecito) (1) Figure: Block diagram and basic floor plan of the Montecito [1.5]

  36. 10.1.4 Dual-core Itanium 2 (Montecito) (2) Figure: Block diagram of the Itanium 2 processor [1.12]

  37. 10.1.4 Dual-core Itanium 2 (Montecito) (3) Figure: Block diagram of the Montecito McNairy C. and Bhatia R., „Montecito,” IEEE Micro, March-April 2005, pp. 10-20

  38. 10.1.4 Dual-core Itanium 2 (Montecito) (4) Figure: New features of Montecito Source: Intel

  39. 10.1.4 Dual-core Itanium 2 (Montecito) (5) Core Figure: Floor plan of Montecito [1.14]

  40. 10.1.4 Dual-core Itanium 2 (Montecito) (6) Montecito (90 nm) Madison (130 nm) (Inthe figure reduced to 90 nm) L2: 256 KB, L3: 9 MB L2I: 1 MB, L2D: 256 KB, L3: 12 MB Figure: Contrasting Itanium 2 Madison and Montecito (at the same feature size) [1.14] Further source: Krewell K., „Best Servers of 2004,” Microprocessor Report, Jan. 2005, http://h10018.www1.hp.com/wwsolutions/misc/docs/2004_Server_Processor_of_Year.pdf

  41. 10.1.4 Dual-core Itanium 2 (Montecito) (7) Figure: Contrasting die sizes and floor plans of Itanium processors Source: DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf

  42. 10.1.4 Dual-core Itanium 2 (Montecito) (8) Series Dual-Core Itanium 2(Montecito) Models 9010 9015 9020 9030 9040 9050 Stepping Introduced 7/2006 Technology 90 nm Die size 596 mm2 Nr. of transistors 1720 mtrs fc [GHz] 1.6 1.40 1.42 1.6 1.6 1.6 L2 1 MB I$ + 256 KB D$ per core L3 2*3 MB 2*6 MB 2*6 MB 2*4 MB 2*9 MB 2*12 MB f HT FSB (16 B wide) [MT/s] 400 533 533 533 533 TDP [W] 75 104 104 104 104 104 Socket PAC 611 64-bit HT ED (Silvervale) VT Cache safe EIST DBS Table: Main features of the dual-core Itanium 2 line [1.8], [1.9]

  43. 10.1.5 Quad-core Itanium 2 (Tukwila) (1) Figure: Expected features of the quad-core Tukwila [1.8]

  44. 10.1.5 Quad-core Itanium 2 (Tukwila) (2) Figure: Preliminary die shot of Tukwila [1.11]

  45. 10.1 Literature (1) x86 multicore processors [1.1] Bhandarkar D., „Energy Efficient Performance: The Next Frontier,” Oct. 2006, http://download.intel.com/technology/eep/fall_microprocessor_forum_2006.pdf [1.2]Brookwood N., The Role of intellignet Desing in the Evolution of Multi-Core Processors,” Febr. 2006. http://www.insight64.com/downloads/IntelligentDesign.pdf [1.3]Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,” http://www.hotchips.org/archives/hc17/3_Tue/HC17.S8/HC17.S8T1.pdf [1.4]Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,” http://idfemea.intel.com/moscow/download/keynotes_and_tis/Li_Babayan_en.pdf [1.5]Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf [1.6]Shimpi A. L. and Wilson D., Intel Pentium 4 6xx and 3.73EE,” Febr. 2005, http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2353&p=3 [1.7]Smith S.L. and Valentine, B.,”Intel Core Microarchitecture,” March 2006, http://download.intel.com/pressroom/kits/press/core2/ NGMA%20IDF%20Press%20Mar%208%20PDF%20Set.pdf [1.8]- Related Intel Datasheets, http://www.intel.com/design [1.9]- Wikipedia

  46. 10.1 Literature (2) Montecito [1.10]DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf [1.11]Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004, http://www.decus.de/sig/vms/TUD_2004/INTEL.PDF [1.12]McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp. 44-55 [1.13] McNairy C. and Bhatia R., „Montecito: A Dual-Core, Dual-Thread Itanium Processor,” IEEE Micro, March-April 2005, pp. 10-20 [1.14]Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,” Proc. ISSCC, 2005, pp. 182-183, [1.15]Naffziger S. et al., The Implementation of a 2-Core, Multi-threaded Itanium Family Processor, IEEE Journal Solid-State Circuits, Vol. 41, No. 1, Jan. 2006, pp. 197-209 [1.16]Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf [1.17]- „Inside the Intel Itanium 2 Processor,” Technical White Paper, July 2002, HP Corp. [1.18]- Related Intel Datasheets, http://www.intel.com/design/itanium2/documentation.htm