1 / 15

LOW COST FPGA IMPLEMENTATION OF TRACKING SYSTEM FROM USB TO VGA

Presented by: Alon Tirosh & Jonathan Ezroni. LOW COST FPGA IMPLEMENTATION OF TRACKING SYSTEM FROM USB TO VGA. Supervisor: Mike Sumszyk. Characterization presentation. From a one to a bi-semester project.

hanzila
Download Presentation

LOW COST FPGA IMPLEMENTATION OF TRACKING SYSTEM FROM USB TO VGA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Presented by: AlonTirosh & Jonathan Ezroni LOW COST FPGA IMPLEMENTATION OF TRACKING SYSTEM FROM USB TO VGA Supervisor: Mike Sumszyk Characterization presentation

  2. From a one to a bi-semester project This is a one semester project, focusing on implementing a tracking algorithm on a low cost FPGA. Project may be extended to be bi- semesteral focusing on the algorithm implementation. One Semester Bi- Semester

  3. Agenda • Project Objectives. • Algorithm. • HW vs. Software. • SoPC overview. • NIOSII Performance. • Memory Considerations • Timing Considerations Tracking block interface. • System Architecture. • Algorithm Implementation. • Timeline.

  4. 1.Project Objectives • ConfigureSoPC including: I/O, memory, processor, bus and peripherals. • Implementtracking algorithm via code in C running on Nios II softcore and via verilog code. The hardware implementation will deal with the computing demanding part of the algorithm. • Producemoving red box enclosing the moving object and aggregate it to the input video stream.

  5. 2.Algorithm • Motion image computation • Mass center computation • Prediction of next mass center (Kalman filter or more simple algorithm)

  6. 3.Hardware vs. Software • Hardware: • RGB2gray, temporal derivative, mass center calculation. • Software: • center of mass prediction Easy Per Pixel Calculations Difficult to implement 1 calculation Per frame

  7. 4.SoPC Overview • DE2 Altera board. • Cyclone II FPGA. • Nios 2 Softcore. • Avalon Switch fabric. • Environment: • SoPC builder. • Quartus II. • IDE II. • ModelSim.

  8. 5.Nios II Performance

  9. 6.Memory considerations Cyclone II has 483Kbits for our use. After compilation of a basic design which includes NIOS II (s - version) with 32K ram, only 211Kbits remains-less than one frame. Hence, there is a need for other memory resources. Flash memory is very slow in write cycles, and with limited lifespan: ~ 100K write cycles (less then 2 hours of video).

  10. 6.Memory considerations • 0.5 MB SRAM is not enough for possible extended image resolution (640x480). • 8 MB of SDRAM will be enough for: 160x120x3x3 = 172,800 Bytes which is the current plan. Extended image resolution.

  11. 7.Timing considerations • VGA output works at 30 bits/clk. • 160x120x15=188000clks/sec~0,3Mhz • NIOS II(s) MIPS/0.3Mhz = 57/0.3= 190. • NIOS II(f) MIPS/0.3Mhz = 105/0.3= 350. • NIOS II(e) MIPS/0.3Mhz = 22/0.3=73. ~ 190/350/73 assembly operations- Instructions per pix. • USB 2.0 is asynchronous. It supports up to 480 Mbits/sec transfer rate 160x120x15x24 = 6. 9 Mbits/sec

  12. 8.System Architecture DE2 Board Cyclone II Nios II Soft Processor Internal memory Custom HW Avalon Switch Fabric USB 2.0 Interface DMA SDRAM INTERFACE VGA controller 15 fps video stream Philips ISP1362 (USB 2.0- device) SDRAM D/A VGA Host

  13. Cyclone II 8.2 DATA FLOW Philips ISP1362 UBS 2.0 controller PC Custom HW NIOS SDRAM DMA ADD Box Boundaries • RGB ->BW • Subtract between 2 pixels • Update of center of mass coordinates • Integrate to NIOS VGA Controller FIFO VGA D/A DE2 Display

  14. 9.MEMORY SCHEME Input stream Tracking calculations SDRAM t+1 t t-1 Box Adder Output stream VGA Controller

  15. 10.TIMELINE UP TO THE MIDTERM

More Related