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Title Slide. GAIA System Solutions, Inc. System Software and Soc Engineering. Software Re-work Costs $$$.

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  1. Title Slide GAIA System Solutions, Inc. System Software and Soc Engineering

  2. Software Re-work Costs $$$ “The cost of reworking errors in programs becomes higher the later they are reworked in the process, so every attempt should be made to find and fix errors as early in the process as possible.” - Michael Fagan, 1976

  3. Standard Sequential System Development Process … Architectural Specification Hardware Development Chip Fabrication Software Development Final Integration Total Development Time 24 months* *In the case of a major cell-phone manufacturer

  4. Replace by Concurrent System Development Process with VaST Executable Architectural Specification Saved 9 months* Software Development Hardware Development Chip Fabrication *In the case of a major cell-phone manufacturer With VaST! Final Integration With VaST: The model is both fast and accurate enoughfor architectural exploration & software development

  5. Graphical Test Bench EEPROM File Vast Cycle Accurate Virtual Platform CAN Timer Dev I/O Sys Timer Mem CPU SPI EE Dev XCVR Dev Dev A/D SCI Input Files Sensor Ctrl Micro Debugger Typical Real-Time Embedded Control Platform

  6. Cycle Accurate Simulation What is it? • Behavioral models of processors and peripheral devices • - same “look and feel” as hardware • Load and execute same software code as bench (single-board computer + ICE) • Same instruction and cycle count as bench VaST Technology proven for several automotive projects: • RISC32 Platform + sensor models • Full system simulation at more-or-less bench speed

  7. Cycle Accuracy is Required for Real-Time Software Development • Allows full SW development and Verification • Virtual “Bench on the desktop” (worldwide) • Regression/unit testing – Scripting for SW tests and release • Visibility inside Virtual Platforms • Standard Software Debugger (breakpoints, trace, etc.) • Full Hardware-Software Debugger (Metrix) • Benefits • SW benches will become almost all “virtual” • Software bench cost 1/2 $$ of hardware bench • SW developed independently of HW (shorten long pole) • Excellent warnings and analysis tools: • better than bench visibility • Test full system before commitment to silicon • Guaranteed accuracy in function and timing

  8. Current Cars RT Control Apps Net Comms s/w ECU RTOS ECU Today, Software Dominates Cost of Delivering a System RT Apps Comms s/w RT Operating System ECU Early Electronically Controlled Cars Electronics Content: 1960: ~1%          1983: ~5%          2003: ~35%          Software is estimated to be 40%-60% of electronics cost

  9. Nothing Ships Until Software Development is Complete Executable Architectural Specification Software Development Architectural Specification Hardware Development Chip Fabrication Software Development Hardware Development Chip Fabrication Without VaST Total Development Time 24 months* With VaST! Saved 9 months* Final Integration *In the case of a major cell-phone manufacturer Final Integration

  10. CoMET and METeor from VaST Xscale processor Xscale processor Memory Memory Timer Timer DMA controller DMA controller Interrupt controller Interrupt controller Platform Creation and Analysis Embedded Software Development

  11. Linux Console ARM926E MeTRIX Memory Timer DMAC INTC PMU GPIO Exploration: Measuring a Virtual Platform Running Linux • Linux running on ARM926E instrumented with many measures

  12. TIMER MIPS TX19 core ARM926E CPU Interrupt Controller Interrupt Controller Serial Link Memory Controller DMA Controller Memory Controller UART UART Memory Model Memory Model ARM926E MIPS TX19 Debugging a Dual Processor (ARM + MIPS) Platform MIPS Insight Debugger ARM AXD debugger

  13. VaST’s CoMET& METeor Fast! Accurate! • Accurate enough for real-time apps • Runs same binary as final chip • Explore, develop, test & debug • Do co-verification against final software • Fast enough for software development

  14. Cycle Accuracy Required for System Simulation • Build and Quantitatively Evaluate Real-Time Platform Architectures • Winning Virtual Platforms are chosen after running a large numbers of big software tests assessing function & time • There are many thousands of complex hardware-software trade-offs decisions required to build competitive hardware platforms • Real-time platform architectures must run large amounts of software efficiently with timing accuracy • Full observability (state & time) inside Virtual Platforms is needed • Requires ability to measure arbitrary interactions between hardware and software (Metrix) • Benefits • Quantitatively assess and architect “optimal” hardware platforms • Calculate accurate platform performance and power consumption, 12-18 months prior to availability of silicon • Develop a family of systems to meet market demand for 3-5 years • Guaranteed accuracy in function and timing

  15. ArchitecturalExploration 8-bit MPU Clock Gen. Serial Comms Interrupt Controller A2D Convert RAM ROM General I/O Bus Interface LowVoltInhibit Virtual bus InterruptTimer EEPROM Virtual Platform Physical Prototype Power Consumption Cost Speed

  16. What’s wrong with ISSs and SBCs? TOO SLOW! Instruction Set Simulation Software developers can’t use anything below 10 MIPS in their everyday edit-compile-debug cycle. TOO EXPEN$IVE! Nobody wants to pay to supply a hardware mock-up like this for every programmer on their team.

  17. VaST’s CoMET Fast and Accurateenough to… • Simulate complex systems (incl. SoCs) – running lots of software • Do quantitative architectural analysis • Evaluate real-time performance • All on any industry-standard PC!

  18. Revolutionary Modeling Technology • Pure software solution • Cycle accurate processor modeling • Cycle accurate bus modeling • Model internal performance attributes Cache misses Bus congestion Pipeline stalls Write back buffering 100x-1000x faster than ISSs! • Fast: Up to 200 MIPS VaST makes virtual platforms practical

  19. System System System System I I I I I Micro- Processor MC68HC08 MC68HC08 Integration Integration Integration Integration N N N N N T T T T T Clock Clock Clock Clock Low Voltage Low Voltage Low Voltage Low Voltage C C C C C Generator Generator Generator Generator Inhibit Inhibit Inhibit Inhibit RAM RAM RAM RAM RAM ROM ROM ROM ROM ROM Configuration Configuration Configuration Configuration Configuration Computer Computer Computer Computer Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Register Register Register Register Register Watchdog Watchdog Watchdog Watchdog Virtual Bus Virtual Bus Serial Serial Serial Serial Comms Comms Comms Comms Interface Interface Interface Interface EEPROM EEPROM EEPROM EEPROM Timer Timer Timer Timer General General General General Interface Interface Interface Interface Purpose I/O Purpose I/O Purpose I/O Purpose I/O Programmable Programmable Programmable Programmable Analog Analog Analog Analog - - - - Digital Digital Digital Digital Interrupt Timer Interrupt Timer Interrupt Timer Interrupt Timer Converter Converter Converter Converter Real Case StudyProblems Found while using VaST Platform • Computer-Operating-Properly watchdog reset processor in error • Software segment not being initialized to zero causing OS halt • Stack overrun • Memory-fail register was not being reset following memory error • Math overflow problem causing late deployment of airbag by 1 second • Math overflow problem in timer code • Accelerometer device-driver reading wrong register • Bootstrap switching to PLL clock before PLL running • Programmable timer initialized incorrectly • Asymmetrical rounding errors

  20. Executable Specification Simulink Stateflow UML Statechart Forms, Z FSM Peripheral Device Builder Software “C/C++” Code Library Hardware Library Translate Common Test Bench Architecture Exploration VaST CoMET + PCT Cycle Accurate Simulation production software SW HW Vast Comet/ Meteor Virtual Platform Controlling Real Subsystems HWIL Advanced System & SoC Development Process

  21. Simulink Abstract Specification Simulink Abstract Specification Abstract Specification Network Interface Network Interface Network Interface Network Interface Network Interface UML Abstract Specification Abstract Specification System Requirements Discovery from Architectural Specification & Experimentation Ethernet/CAN Bus protocol Build & Simulate using CoMET

  22. CoDec Simulink model (C-code) UML / Simulink Abstract Specification XScale Electronic Interface INTC Network Interface Timer Register Register MV Linux Console Abstract Spec.  Target Code Memory CAN Bus Interface XScale MeTRIX Memory CAN Bus I/F Electronic Interface UML Model (target code) RF Simulink model (C-code) Display Timer Register Register Timer DMAC INTC PMU GPIO Refining Specification: Mapping Abstract Subsystems to Partial Platforms Ethernet/Can bus protocol Simulate using CoMET/METeor

  23. Linux Console Notebook Host Computer ARM7 UART Host Ethernet Socket Host Ethernet Driver Timer IntC Virtual Host Ethernet Ctrl Memory (Ethernet snooping Code) Host Pipe Virtual Platform Target Software on Virtual Platform Snooping Real Ethernet packets Ethernet Switch

  24. Summary VaST: CoMET & METeor • VaST covers all stages of the system development process: • Specification, Architectural assessment, design, realization, HWIL testing • VaST uses industry standard notations: • Hardware: SystemC, C, C++, Verilog/VHDL, UML, Simulink & VaST AMPI • Software: C, C++, UML, Stateflow/Statechart • Mechanical/Analog: Simulink, UML, C/C++ & VaST AMPI • VaST Cycle-Accurate Virtual Platforms enable the development, 12-18 months in advance of silicon, of: • Correct and effective real-time architectures, and • Efficient real-time embedded software • VaST addresses the big problem: 30% and 80% of cost of developing complex real-time SOC products is due to software: • Software is always on the critical path • Real-time systems require cycle accurate Virtual Platforms: • Software developed must be guaranteed to run on the real silicon • VaST’s Virtual Platforms are 50 – 1,000 times faster than ISS-based platforms

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