Topics

1. Topics Aliases Subprograms Generics & Configurations

2. Aliases An alternate name for name items • Can significantly improve the readability of VHDL codes by using a shorthand notation for long names. • Provides a mechanism to refer to the same named item in different ways. Advanced Topics on VHDL

3. Aliases An example: signalS: BIT_VECTOR (31downto0); Can represent: Sign Exponent Mantissa 31 30 23 0 Or: OP Reg Base Offset 31 26 23 18 0 Advanced Topics on VHDL

4. Aliases Syntax: alias identifier [ : identifier-type] is item-name; Optional “signature” portion alias identifier [ : identifier-type] is item-name [signature]; Advanced Topics on VHDL

5. Object aliases Constant Signal Variable File Non-Object aliases Function names Literals Type names Attribute names Aliases Except: labels, loop parameters, and generate parameters Advanced Topics on VHDL

6. Aliases Object aliases: Examples : constantnumber_of_bytes : integer :=4; alias N : integer is number_of_byptes; Advanced Topics on VHDL

7. Example: Suppose we need to use objects from two different packages, work.alu_types.all and work.io_types.all, and each declare a constant named data_width with different values. If we include packages as follows: • Then we have to refer to them as: • work.alu_tpes.data_width • work.io_types.all.data_width It’s not convenient ! Aliases Object aliases: Advanced Topics on VHDL

8. Aliases Object aliases: We can avoid this by: Introducing two alias declarations into our model! Advanced Topics on VHDL

9. function names literal type name Aliases None-object aliases: Example: Advanced Topics on VHDL

10. Aliases With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. In this way, we break down complex data structures into simpler parts that can be accessed directly. Advanced Topics on VHDL

11. function names Aliases An example: Advanced Topics on VHDL

12. Aliases With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. In this way, we break down complex data structures into simpler parts that can be accessed directly. Notice: we are NOT defining a new data type. However, there are real subtypes. Advanced Topics on VHDL

13. Aliases Signature alias identifier [ : identifier-type] is item-name [signature]; The “signature” portion is optional. • Used for • Subprograms • Enumeration literals Advanced Topics on VHDL

14. Aliases Syntax: alias identifier [ : identifier-type] is item-name [signature]; The “signature” portion is optional. Signature’s syntax rule: [ type_mark ,… return type_mark ] Advanced Topics on VHDL

15. function names literal type name Aliases None-object aliases: Example: Advanced Topics on VHDL

16. Topics Aliases Subprograms Generics & Configurations

17. Subprograms • Like other programming languages, VHDL provides subprogram facilities in the form of functions and procedures. • VHDL also provided a package facility for collecting declarations and objects into modular units. • Packages also provide a measure of data abstraction and information hiding. Advanced Topics on VHDL

18. Subprograms • Two steps: • First they must be declared; • Then they can be called elsewhere. Advanced Topics on VHDL

19. Subprograms Modes: Advanced Topics on VHDL

20. Subprograms: functions • Functions: • Can be used within an expression; • Can be used to describe frequently used sequential algorithms; • Return a single value; • Execute in zero simulation time (no WAIT allowed). Advanced Topics on VHDL

21. mode Subprograms: functions Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ]; Where parameter_interface_list is: ([ constant | variable | signal ] identifier {, …} : in type_indication [ := static_expression ] ) { ,…} Advanced Topics on VHDL

22. Subprograms: functions Example: Advanced Topics on VHDL

23. Subprograms: functions Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ]; Call: identifier [(parameter_association_list )] Advanced Topics on VHDL

24. Subprograms: functions Example: Advanced Topics on VHDL

25. Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ]; Subprograms: functions • By default, functions are declared as pure; • In pure functions, the only accessible data are the input arguments; and the only returned information from this function is the returned value. Pure functions do not have access to objects outside the function. • VHDL’93 introduces impure declaration; • Impure functions must be explicitly declared; • Impure functions can modify data outside their own scope. Advanced Topics on VHDL

26. Subprograms: functions Example: The file bit_file is an outside object. Since the function is impure, accessing to the file bit_file is possible. Advanced Topics on VHDL

27. Subprograms: functions Usages of functions: • Returning a value in an expression. • Conversion functions. ------ to convert an object of one type to another • Resolution functions. ------ to resolve bus contention on a multiply-driven signal Advanced Topics on VHDL

28. Subprograms: functions • Conversion functions. are used to convert an object of one type to another to allow mapping of signals and ports of different types. This type of situation usually arises when a designer wants to make use of an entity from anther design that uses a different data type. Advanced Topics on VHDL

29. Subprograms: functions • Resolution functions are used to return the value of a signal when the signal is driven by multiple drivers. It is illegal in VHDL to have a signal with multiple drivers without a resolution function attached to it. A resolution function has a signal-argument input (consists of an unconstrained array of driver values for the signal) and returns a single signal value. Advanced Topics on VHDL

30. Subprograms: procedures • Procedures: • Can be used to partition large behavioral descriptions into modular sections; • A procedure call may be a sequential or concurrent statement; • Arbitrary number of parameters of any possible direction ( in / out / inout ); • May or may not execute in zero simulation time. Advanced Topics on VHDL

31. Subprograms: procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Where parameter_interface_list is: ([ constant | variable | signal ] identifier {, …} : mode type_indication [ := static_expression ] ) { ,…} Advanced Topics on VHDL

32. Subprograms: procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Call statement: [ label : ] procedure_name [ (parameter_association_list)]; Advanced Topics on VHDL

33. Subprograms: procedures Example: Advanced Topics on VHDL

34. Subprograms: procedures Default Values in the parameters: When the procedure is called, we can use either leave it out in the caller’s parameter list, or use keyword ‘open’. Advanced Topics on VHDL

35. or or Subprograms: procedures Example: Advanced Topics on VHDL

36. Subprograms: procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Call statement: [ label : ] procedure_name [ (parameter_association_list)];; Advanced Topics on VHDL

37. call_proc: p ( s1, s2, val ); call_proc: process is begin p ( s1, s2, val ); wait on s1, s2; end process call_proc; Subprograms: procedures Concurrent Procedure Call Statements: are equivalent to the same procedures with a wait statement, whose sensitivity clause includes the signals mentioned in the parameter list. The equivalent procedure: A concurrent procedure call: Advanced Topics on VHDL

38. Subprograms: procedures Function: encapsulates a collection of statements that compute a result Þ generate an expression Procedure: encapsulates a collection of sequential statements to execute Þ generate a statement Advanced Topics on VHDL

39. Generics&Configurations

40. Generics Can we write general models instead of making specific models with VHDL ? Advanced Topics on VHDL

41. Generics Motivation: • Oftentimes we want to be able to specify a property separately for each instance of a component. • VHDL allows models to be parameterized with generics. • Allows one to make general models instead of making specific models for many different configurations of inputs, outputs, and timing information. • Information passed into a design description from its environment. Advanced Topics on VHDL

42. A generic Generics AND gate entity AND_GATE is generic ( N: natural := 2 ); port ( A: in bit_vector (1 to N ); Z: out bit); end AND_GATE; architecture generic_ex of AND_GATE is begin process (A) variable AND_OUT:bit; begin AND_OUT := ‘1’; for k in 1 to N loop AND_OUT := AND_OUT and A(k); exit when AND_OUT = ‘0’; end loop; Z<=AND_OUT; end process; end GENERIC_EX; Advanced Topics on VHDL

43. Generics • A generic declares a constant object of mode in (read only); The value of this constant can be specified as a static expression globally: • Then it can be used in the entity declaration and its corresponding architecture bodies. • The value of a generic must be determined at elaboration time (explicitly specified at least once). Advanced Topics on VHDL

44. Generics The value for a generic may be specified • in an entity declaration; • in a component declaration; • in a component instantiation. Advanced Topics on VHDL

45. Generics entity ANOTHER_GEN_EX is end; archiecture GEN_IN_COMP of ANOTHER_GEN_EX is component NAND_GATE generic (M: INTEGER); port (A: in bit_vector(M downto 1); z: out bit); end component; component AND_GATE generic (N: natuaral := 5); port (A: in bit_vector(1 to N); Z: out bit); end component; signal S1, S2, S3, S4: bit; signal SA: bit_vector( 1to 5); signal SB: bit_vector( 2 downto 1); signal SC: bit_vector(1 to 10); signal SD: bit_vector(5 downto 0); begin N1: NAND_GATE generic map (6) port map (SD, S1); --N2: NAND_GATE port map (SB, S2); A1: AND_GATE generic map (N => 10) port map (SC, S3); A2: AND_GATE port map (SA, S4); end GEN_IN_COMP; component declarations component instantiations Advanced Topics on VHDL

46. Generics Notes: • Generic information is static ------it can not be changed during the simulation. • Generic value is instance-specific ------different instances of the same component can have different values. Advanced Topics on VHDL

47. Configurations • Why we need configurations ? It may be convenient to specify multiple views for a single entity and use any one of them for simulation. For example, there are three architecture bodies, called FA_BEH, FA_STR, and FA_MIXED, corresponding to an entity FULL_ADDER. We can select any of them for simulation by specifying an appropriate configuration. Advanced Topics on VHDL

48. Configurations • Configurations A VHDL description may consist of many design entities, each with several architectures, and organized into a design hierarchy. The configuration does the job of specifying the exact set of entities and architectures to use, in other words, binding component instances to entities. Advanced Topics on VHDL

49. Configurations • Configurations • Specify which architectures to use for a particular component • Specify which parameter values to use for a particular component Advanced Topics on VHDL

50. Configurations • A configuration is therefore used to bind the following pairs: • An architecture body to its entity declaration • A component with an entity • Definition: • Associating an architectural description with a component in a structural model. Advanced Topics on VHDL