1 / 11

Single-cycle datapath

0 M u x 1. Add. PC. 4. Add. Shift left 2. PCSrc. RegWrite. MemToReg. MemWrite. Read address. Instruction [31-0]. I [25 - 21]. Read register 1. Read data 1. ALU. Read address. Read data. 1 M u x 0. I [20 - 16]. Zero. Read register 2. Instruction memory. Read

gianna
Download Presentation

Single-cycle datapath

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 0 M u x 1 Add PC 4 Add Shift left 2 PCSrc RegWrite MemToReg MemWrite Read address Instruction [31-0] I [25 - 21] Read register 1 Read data 1 ALU Read address Read data 1 M u x 0 I [20 - 16] Zero Read register 2 Instruction memory Read data 2 0 M u x 1 Result Write address 0 M u x 1 Write register Data memory Write data Registers I [15 - 11] ALUOp Write data MemRead ALUSrc RegDst I [15 - 0] Sign extend Single-cycle datapath don’t care?

  2. R-type execution R-type writeback Op = R-type Instruction fetch and PC increment Branch completion Register fetch and branch computation Op = BEQ Memory write Effective address computation Op = SW Memory read Register write Op = LW/SW Op = LW FSM for multicycle control unit • Clock triggers transitions • #cycles = length of longest graph cycle

  3. Executing a beq instruction • How many cycles? • Instruction fetch (memory) • PC increment by 4 (ALU) • Register fetch (register file) • Register comparison (ALU) • Branch target computation (ALU)

  4. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) • Register fetch (register file) • Register comparison (ALU) • Branch target computation (ALU)

  5. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) before next IF • Register fetch (register file) • Register comparison (ALU) • Branch target computation (ALU)

  6. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) merge into one • Register fetch (register file) • Register comparison (ALU) • Branch target computation (ALU)

  7. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) • Register fetch (register file) before comparison • Register comparison (ALU) • Branch target computation (ALU)

  8. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) • Register fetch (register file) before comparison • Register comparison (ALU) before finding target • Branch target computation (ALU)

  9. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) • Register fetch (register file) before comparison • Register comparison (ALU) before finding target • Branch target computation (ALU) so, must be last 4 cycles 

  10. Executing a beq instruction • How many cycles? • Instruction fetch (memory) must be first • PC increment by 4 (ALU) • Register fetch (register file) before comparison • Register comparison (ALU) before finding target • Branch target computation (ALU) so, must be last 4 cycles  3 cycles 

  11. Optimistic execution • Wasteful, bu no harm doing the computation early. • If the branch is not taken, we can just ignore the ALU result. • This idea is also used in more advanced CPU design techniques • branch prediction

More Related