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MIPS Datapath (Single Cycle and Multi-Cycle) PowerPoint Presentation
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MIPS Datapath (Single Cycle and Multi-Cycle)

MIPS Datapath (Single Cycle and Multi-Cycle)

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MIPS Datapath (Single Cycle and Multi-Cycle)

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  1. MIPS Datapath(Single Cycle and Multi-Cycle) CIS 314 Fall 2005

  2. Basic MIPS Implementation • For a limited subset of the MIPS instructions • Memory reference: LW and SW • Arithmetic-logical: add, sub, and, or, slt • Branch: beq • Hardware components: PC, registers, memory units, ALU, multiplexors, decoders CIS 314 Fall 2005

  3. Single Cycle v. Multi-Cycle • Single cycle is not realistic - just for understanding of the implementation. • Single cycle: one (long) clock cycle to process each instruction • Multi-cycle: divide the processing of each instruction into 5 stages and allocate one clock cycle per stage CIS 314 Fall 2005

  4. Major Functional Units CIS 314 Fall 2005

  5. Functional Units and Control Lines CIS 314 Fall 2005

  6. Fetch instruction and increment PC CIS 314 Fall 2005

  7. Memory transfer -- R-type instructions CIS 314 Fall 2005

  8. Computing branch condition and target address CIS 314 Fall 2005

  9. Single cycle and control unit CIS 314 Fall 2005

  10. Single cycle plus jump CIS 314 Fall 2005

  11. 4004 4004 4004 4004 0 0 1 x 0 0 0 10 000000 0 0 1 00101 00101 0 x 01111 0 0 00110 xxxxxxx 00001 10000 10 00110 00110 10000 1 0 1000000000100000 100000 10 Example of execution XXXX 1111111111111111100000000010000000 4004 4000 000000 00101 01111 10000 00000 100000 00110 Instr: add $s0, $a1, $t7 Field: op rs rt rd shamt funct M. Code: 000000 00101 01111 10000 00000 100000 PC: 0 x 4000 11111111111111111000000000100000 CIS 314 Fall 2005

  12. You’d better do this (aka Suggested Exercises) • Repeat the example of execution for: • lw $t3, 16($t2) • sw $t3, 16($t2) • addi $t1, $s2, $v0 • beq $t3, $s0, gothere • jmp gothere • jr $ra CIS 314 Fall 2005

  13. Multicycle Datapath • Break the operations on an instruction into a series of 5 steps. • One clock cycle per step • Instruction Fetch (IF) • Instruction Decode (ID) • Execute (EX) • Memory Access (MEM) • Write Back (WB) CIS 314 Fall 2005

  14. Multicycle Datapath • HW changes: • Single memory unit for both instructions and data • Single ALU for all arithmetic operations • Extra registers needed to hold values between each steps • Instruction Register (IR) holds the instruction • Memory Data Register (MDR) holds the data coming from memory • A, B hold operand data coming from the registers • ALUOut holds output coming out of the ALU CIS 314 Fall 2005

  15. Extra hardware for multicycle datapath CIS 314 Fall 2005

  16. Multicycle datapath CIS 314 Fall 2005

  17. Complete multicycle datapath CIS 314 Fall 2005

  18. Multicycle Datapath: the 5 steps CIS 314 Fall 2005