A 10 bit,100 MHz CMOS Analog-to-Digital Converter - PowerPoint PPT Presentation

a 10 bit 100 mhz cmos analog to digital converter n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
A 10 bit,100 MHz CMOS Analog-to-Digital Converter PowerPoint Presentation
Download Presentation
A 10 bit,100 MHz CMOS Analog-to-Digital Converter

play fullscreen
1 / 27
A 10 bit,100 MHz CMOS Analog-to-Digital Converter
271 Views
Download Presentation
georgio-betagh
Download Presentation

A 10 bit,100 MHz CMOS Analog-to-Digital Converter

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. A 10 bit,100 MHz CMOS Analog-to-Digital Converter

  2. Outline • Introduction • High Speed A/D Converter Architectures • Proposed A/D Converter Architecture • Circuit Design and Simulations • Prototype Chip Test Results • Conclusion • Research Plan

  3. Applications of High Speed High Resolution A/D Converter • High frequency digital data communication • Waveform acquisition instruments • Medical Imaging • Video Signal Processing

  4. Increasing DSP complexity in communications systems

  5. High Resolution High Speed CMOS A/D Converters

  6. Conceptually most straightforward 1. Highest possible speed 2. Resolution: 8-10bits Disadvantages 1. 2 comparators requires So, Hardware complexity grows exponentially with resolution 2. Large power dissipation and input capacitance Fully Parallel(Flash) A/D Converter

  7. Two-Step A/D Converter • Less hardware complexity than Flash type • Digital error correction is possible • Disadvantages: • Requires inter-stage amplifier (longer conversion time) • Requires multiple clocks per conversion

  8. Multi-Stage Pipeline A/D Converter • Well-suited to CMOS, as residue amplifier has built-in S/H • May repeat same blocks in cascade • Approximately linear hardware cost with resolution • Limitations: 1. Residue amplifier settling is speed bottleneck 2. Linearity determined by input S/H and residue formation

  9. Parallel Pipelined A/D Converter • Conversion rate increases with the number of channels • Input S/H must acquire singal at full Nyquist bandwidth • Performance ultimately limited by: 1. Timing skews and jitter between channels 2. Mismatch in gain, offset and full scale between channels

  10. Effect of Sampling Timing Offset in Parallel Pipelined A/D Converter

  11. SNR with gain mismatch 2 channel pipeline ADC

  12. Design Specification • 10 bit resolution • 100 MHz conversion rate • Fully Differential Implementation • 1.0V input full scale • 1.0m n-well CMOS technology with linear capacitance option • 1.0 W power dissipation • 2-channel 3-stage pipelined architecture • 4 bit/stage conversion • Parallel Pipeline Switch Cap. Residue Amplifier • Resistor Ladder DAC • On-chip clock buffer

  13. Detail Block Diagram of Architecture

  14. Timing Diagram of S/H, 4-bit ADDA, and RA

  15. Schematic of Non-resetting S/H • Equivalent to two resetting S/H • Following stage can obtain the valid data for full period(10ns) • Disadvantage: • Ch and Cd increase a time constant

  16. Simulated Dynamic Performance of S/H

  17. 4-bit AD-DA Block Diagram

  18. Residue Amplifier • Gain of 2 Residue Amplifier: • Generate a residue (subtract DAC output from S/H output) • Reduce inter-channel offect  Offset Cancellation Scheme • Gain of 4 Residue Amplifier: • Reduce inter-channel offset  Offset Cancellation Scheme • Compensation capacitor added ot stabilized loop when sampling

  19. Digital Circuit in ADC

  20. Clock Generation Circuit

  21. Measured SNDR,THD,and SFDR at 500 KHz input

  22. Measured Signal / (Noise+Distortion) at 4, 50 & 95 MHz Sampling rate

  23. Power Dissipation • Total power dissipation = 1.1W @ 95MS/s

  24. Layout Design Issues: Clock distribution Reduce the Offset in Residue Amplifier Floor Plan of A/D Converter

  25. Summary of A/D Characteristics

  26. Conclusions • 10-bit resolution • 95MS/s conversion rate • 1m n-well CMOS technology with linear capacitor option • Spurious tones are less -65db after simple on chip offset cancellation • 1.2W power dissipation @ single 5V • Digital error correction • First 10-bit, 100MS/s CMOS ADC

  27. Research Plan • Investigate further effects of architecture on SFDR • Hope to design 14bit linear input S/H capable of 2.5MHz or higher clock rate • Considerations: • Nonlinearity in interstage of ADC (For example: Offset, Gain, Carpacitor and Resistor mismatch, Timing mismatch ..)