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VLSI Physical Design Concepts for Performance-driven Layout Optimization

Explore VLSI physical design flow, styles (Full custom, Semi-custom, Standard cell, FPGA), and considerations for performance-driven layout like area, time, delay, noise, and power.

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VLSI Physical Design Concepts for Performance-driven Layout Optimization

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  1. Lecture 2 • VLSI Physical Design • VLSI design flow • VLSI physical design • Physical design flow • Design style • Performance-driven physical design VLSI Physical Design

  2. Lecture 2(cont.) • VLSI design flow • Discuss Figure 1.1 (p5) • Discuss Figure 1.2 (p10) VLSI Physical Design

  3. Lecture 2(cont.) • VLSI physical design • Discuss Figure 1.3 (p14) VLSI Physical Design

  4. Lecture 2(cont.) • Physical design flow • Discuss Figure 1.4 (p16) • Discuss Figure 1.5 (p17) VLSI Physical Design

  5. Lecture 2(cont.) • Design style • Full custom • Discuss Figure 1.5 (p17) • Semi-custom • Gate array (Figure 1.8 and 1.7, p22-21) • Standard cell (Figure 1.6, p20) • FPGA (Figure 1.9, p23) VLSI Physical Design

  6. Lecture 2(cont.) • Performance-driven physical design • Layout area • Time • Delay and skew • Noise • Signal coupling and ground bounce • Low power VLSI Physical Design

  7. Lecture 2(cont.) • Reading assignment • Read Chapter 1 and write a two page reading report • Visit Cadence website and find out the tools related to the physical design VLSI Physical Design

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