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1um CMOS Process Baseline Electrical Test Summary. Georgia Tech Microelectronics Research Center. Summary Package Outline. Overall Summary - pages 3 - 8 Front End Summary - pages 9 - 65 test structure description and methodology theoretical expected value measured value results

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1um CMOS Process Baseline Electrical Test Summary


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    1. 1um CMOS Process BaselineElectrical Test Summary Georgia Tech Microelectronics Research Center Georgia Tech Microelectronics Research Center

    2. Summary Package Outline • Overall Summary - pages 3 - 8 • Front End Summary - pages 9 - 65 • test structure description and methodology • theoretical expected value • measured value results • Back End Summary - pages 66 - 110 • test structure description and methodology • theoretical expected value • measured value results Georgia Tech Microelectronics Research Center

    3. CMOS Baseline summary • Overall Summary of CMOS baseline • NMOS transistor yield is 30% for 3um < L < 25um. Below 3um yield falls to 20% due to punch-thru. • PMOS transistor yield is 25% for 3um < L < 25um. Below 3um yield falls to 5% due to punch-thru. • Many front end parameters have median values close to target however standard deviation is high as can be seen in % pass on summary page or in the raw data throughout the presentation. • Contact parameters are the most off target and would be the first area to address in improving the CMOS line. (Contact experiment has since been completed. See separate presentation summary for results). • What is the baseline? • The baseline consists of 5 batches with a total of 37 wafers. Each batch was processed individually and separately between 2001 - 2003 timeframe in the MiRC cleanroom. • Batch 6 showed the best overall performance across all parameters and notably had a 60% NMOS transistor yield and 70% PMOS transistor yield. Georgia Tech Microelectronics Research Center

    4. Front & Back End Summary Contact parameters are the parameters which are most off target, followed by field oxide thickness, NMOS threshold voltage, and M1 serpentine Resistance. Georgia Tech Microelectronics Research Center

    5. Overall Transistor Yield NMOS PMOS Note that transistor yield shows a dependency on channel length. For channel lengths = 3um and greater yield is fairly constant. For channel lengths 2um and lower, the yield degrades due to punchthru. Transistor Yield is defined as threshold voltage, saturation current, and off current all being in control limits for a given die. The % of good die on a wafer can then be calculated and averaged over all of the batches. Georgia Tech Microelectronics Research Center

    6. NMOS & PMOS Off Current (A)W=10 m, L=varying, Log10 scale NMOS PMOS punch-thru Below channel length of 3um, the OFF state current increases rapidly. The current shown is the current from the source due to the bias at the drain. Therefore it is punch-thru. (This data is from batch 6 wafer 6 and is typical of the baseline.) Georgia Tech Microelectronics Research Center

    7. NMOS & PMOS IDS VS. VDS CURVESW/L = 10um/3um NMOS PMOS IDS vs. VDS curves are shown from one of the better performing batches (Batch 6 wafer 1) from a W/L = 10um/ 3um transistor . At, VDS=VGS=5V, NMOS and PMOS saturation current is 1.14mA and 0.35mA respectively. Normalizing for transistor width (W=10um), NMOS and PMOS saturation currents are 0.114mA/um and 0.035mA/um respectively. Georgia Tech Microelectronics Research Center

    8. Subthreshold Slope and Drain InducedBarrier Lowering (DIBL) NMOS PMOS Sub-threshold curves are shown from one of the better performing batches (Batch 6 wafer 1). NMOS and PMOS sub-threshold slopes are both 150mV/decade. NMOS and PMOS DIBL are 10mV/V and 20mV/V respectively. Georgia Tech Microelectronics Research Center

    9. Front End Parameter Summary • Front End Parameters which are analyzed in this presentation are listed below and are covered on slides 7-61. • N+, P+, Poly sheet resistance • Poly CD • Poly COMB leakage • Poly serpentine resistance • NMOS & PMOS gate oxide thickness • N-Well & P-Well field oxide thickness • NMOS & PMOS • Threshold Voltage • Saturation & Linear current • Off current Georgia Tech Microelectronics Research Center

    10. N+ Sheet Resistance Structure 3 5 7 9 1 “wide” structure (216.5 m long x 4.5 m wide) Van der pauw structure 8 10 2 4 6 There are two N+ sheet resistance measurements made. One is made on the “wide” structure, the other is made on the Van der pauw structure. A maximum current of 100mA is forced (IF) between pads 9 and 1 with an applied 1V, and a voltage drop is measured (VM) at pads given in the table below. Georgia Tech Microelectronics Research Center

    11. N+ Sheet Resistance Theoretical Value The N+S/D As Implant has a dose of 5.74E19/cm3 and a junction depth of 1.6um after 1 hour of annealing at 950C. Georgia Tech Microelectronics Research Center

    12. N+ Sheet Resistance Theoretical Value  = q(nn + pp) for N-type material,   qnn   1/ For N+S/D, a 5E15, 160keV As implant is used, and a 1 hr anneal at 950C is performed Therefore n = 5.74E19 cm-3 and xj = 1.6m   1/{(1.6E-19 C)(5.74E19 cm-3 )(~23* cm2/V-s)}  4.7E-3 cm Rs =  / xj = (4.7E-3 cm) / (1.6E-4 cm) Rs= 29.6 / *P.M.Rousseau, et.al., ”A Model for Mobility Degradation in Highly Doped Arsenic Layers”, IEEE Transactions on Electron Devices, vol. 43, p.2025, 1996. Georgia Tech Microelectronics Research Center

    13. N+ Sheet Resistance (/) Measured ValueVan der Pauw Method, Target = 30 / Full Scale  Target = 30 / 0 to 150 / Scale  Georgia Tech Microelectronics Research Center

    14. N+ Sheet Resistance (/) Measured Value Wide structure method, Target = 30 / Full Scale  Target = 30 / 0 to 150/ Scale  Georgia Tech Microelectronics Research Center

    15. N+ Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method Unity line Theoretical Target = 30 /  The Van der pauw method data seems aberrant as it is several orders of magnitude higher than the Wide method and it appears to get worse with higher resistance values. It seems that the Wide method is more accurate as it produces more values closer to the theoretical target. In either case, both methods show there are many die with excessively high sheet resistance. Georgia Tech Microelectronics Research Center

    16. N+ Sheet Resistance (/  ) Measured ValueSummary Mean = 47.8 /  Target = 30 /  Average % Pass = 63% Using the Wide Method data, the mean of all the wafer medians is 47.8 /, excluding wafers with values marked in red. Using a LCL = 3 and UCL = 150, the average % of good die for a given wafer is 61% (no wafers excluded). Georgia Tech Microelectronics Research Center

    17. P+ Sheet Resistance Structure 3 5 7 9 1 “wide” structure (217 m long x 4.5 m wide) Van der pauw structure 8 10 2 4 6 There are two P+ sheet resistance measurements made. One is made on the “wide” structure, the other is made on the Van der pauw structure. A maximum current of 100mA is forced (IF) between pads 9 and 1 with an applied 1V, and a voltage drop is measured (VM) at pads given in the table below. Georgia Tech Microelectronics Research Center

    18. P+ Sheet Resistance Theoretical Value  = q(nn + pp) for P-type material,   qpp   1/ For P+S/D, a 5E15, 30keV B11 implant is used, Therefore n = Cp = 4.6E20 cm-3 and xj = 0.100m   1/{(1.6E-19 C)(4.6E20 cm-3 )(~35* cm2/V-s)}  3.9E-4 cm Rs =  / xj = (3.9E-4 cm) / (1E-5 cm) Rs = 39 / *G.Masetti, et.al., ”Modeling of Carrier Mobility Against Carrier Concentration in Arsenic-, Phosphorus-, and Boron-Doped Silicon”, IEEE Transactions on Electron Devices, vol. 30, p.764, 1983. Georgia Tech Microelectronics Research Center

    19. P+ Sheet Resistance (/)Van der Pauw Method, Target = 39 / Full Scale  Target = 39 / 0 to 120 / Scale  Georgia Tech Microelectronics Research Center

    20. P+ Sheet Resistance (/)Wide structure method, Target = 39 / Full Scale  Target = 39 / 0 to 120 / Scale  Georgia Tech Microelectronics Research Center

    21. P+ Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method Unity line Theoretical Target = 39 / The Van der pauw method data seems aberrant as it is several orders of magnitude higher than the Wide method and it appears to get worse with higher resistance values. It seems that the Wide method is more accurate as it produces more values closer to the theoretical target. In either case, both methods show there are many die with excessively high sheet resistance. Georgia Tech Microelectronics Research Center

    22. P+ Sheet Resistance (/) Measured ValueSummary Mean = 49.3 / Target = 39 / Average % Pass = 48% Using the Wide Method data, the mean of all the wafer medians is 49.3 /, excluding wafers with values marked in red. Using a LCL = 3 and UCL = 120, the average % of good die for a given wafer is 48% (no wafers excluded). Georgia Tech Microelectronics Research Center

    23. Poly Sheet Resistance Structure 3 5 7 9 1 “wide” structure (217 m long x 6 m wide) “narrow 1 CD” Van der pauw structure “narrow 2 CD” 8 10 2 4 6 “narrow 1 CD” structure (202.5 m long x 2 m wide) “narrow 2 CD” structure (245 m long x 2 m wide) Georgia Tech Microelectronics Research Center

    24. Poly Sheet Resistance Theoretical Value Rs = 49 / Georgia Tech Microelectronics Research Center

    25. Poly Sheet Resistance (/)Van der Pauw Method, Target = 49 / Full Scale  Target = 49 / 0 to 150 / Scale  Georgia Tech Microelectronics Research Center

    26. Poly Sheet Resistance (/)Wide structure method, Target = 49 / Full Scale  Target = 49 / 0 to 150 / Scale  Georgia Tech Microelectronics Research Center

    27. Poly Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method Unity line Theoretical Target = 49 / The Van der pauw method data seems aberrant as it is several orders of magnitude higher than the Wide method and it appears to get worse with higher resistance values. It seems that the Wide method is more accurate as it produces more values closer to the theoretical target. In either case, both methods show there are many die with excessively high sheet resistance. Georgia Tech Microelectronics Research Center

    28. Poly Sheet Resistance (/) Measured ValueSummary Mean = 44.3 / Target = 49 / Average % Pass = 53% Using the Wide Method data, the mean of all the wafer medians is 44.3 /, excluding those wafers with values marked in red. Using a LCL = 3 and UCL = 150, the average % of good die for a given wafer is 53% (no wafers excluded). Georgia Tech Microelectronics Research Center

    29. Poly CD Narrow #1 & #2 (m)Target = 2m Full Scale  Full Scale  Georgia Tech Microelectronics Research Center

    30. Poly CD Narrow #1 & #2 (m)Target = 2m 0 to 10m Scale  0 to 10m Scale  Georgia Tech Microelectronics Research Center

    31. Poly CD Narrow #1 & #2 comparison Unity line Target = 2 m There does not appear to be a printing bias between CD Narrow 1 & 2. Georgia Tech Microelectronics Research Center

    32. Poly CD Narrow Summary Mean = 3.4 m Target = 2 m Average % Pass = 56% The mean of all the wafer medians is 3.4 m, excluding those wafers with values marked in red. Using a LCL = 0.1 m and UCL = 6 m, the average % of good die for a given wafer is 56% (no wafers excluded). Georgia Tech Microelectronics Research Center

    33. Poly COMB & Serpentine Structure 3 5 7 9 1 8 10 2 4 6 left comb serpentine COMB & Serpentine #1 COMB & Serpentine #2 (duplicate of #1) Poly CD = 2m Space = 2m serpentine length = 6,764m right comb Georgia Tech Microelectronics Research Center

    34. Poly COMB & Serpentine The serpentine poly line is connected to pad 5 & 10 on structure #2 and pad 1 & 6 on structure #1. The purpose of the serpentine structure is to measure its resistance and monitor for “opens” due to incomplete patterning. The serpentine is long and winding in order to make it susceptible to lithography and etch patterning problems. A poly comb lies on either side of the serpentine poly. The comb is electrically isolated from the serpentine line. The purpose of the comb is to measure leakage current between it and the poly serpentine and monitor for “shorts”. Shorts would be caused by remaining poly electrically connecting the comb to the poly serpentine line. On structure #2, pads 7 & 9 connect to the comb to the left of the serpentine and pad 8 connects to the comb to the right of the serpentine. On the structure #1, pad 3 connects to the comb on the left of the serpentine, and pads 2 & 4 connect to the comb on the right of the serpentine. Georgia Tech Microelectronics Research Center

    35. Poly COMB leakage (A)Target = 1E-12 A A good die from Batch 3, Wafer 4 was compared to a bad die from Batch 5 wafer 4. The findings are presented on the next slide. Georgia Tech Microelectronics Research Center

    36. Poly COMB Good vs. Bad comparison GOOD BAD Batch 3, wafer 4, die (5,8) Batch 5, wafer 4, die (4,6) Space not visible between Poly lines. Lines are shorted together. CONCLUSION: Polysilicon lithography either underdeveloped or underexposed. Not a problem with Etching. Space visible between Poly lines. Georgia Tech Microelectronics Research Center

    37. Poly COMB Summary Mean = 1.3E-12 A Target = 1E-12 A Average % Pass = 66% The mean of all the wafer medians is 1.3E-12A, excluding those wafers with values marked in red. Using a LCL = 0 and UCL = 1E-9, the average % of good die for a given wafer is 66% (not excluding any wafers). Georgia Tech Microelectronics Research Center

    38. Poly Serpentine Resistance ()Target = 166 k Poly CD = 2m serpentine length = 6,764m 6,764m /2m = 3,382 3,382 * (49 /) = 166k  Target = 166k  Georgia Tech Microelectronics Research Center

    39. Poly Serpentine Resistance () Summary Median = 184 k Target = 166 k Average % Pass = 33% The median of all the wafer medians is 184 k, excluding wafers whose values are marked in red. Using a LCL = 16 k and UCL = 497 k , the average % of good die for a given wafer is 47% (not excluding any wafers). Georgia Tech Microelectronics Research Center

    40. Gate & Field Oxide Structure 3 5 7 9 1 100 m x 100 m 8 10 2 4 6 *The PMOS Gate & N-Well Field structures are in a row adjacent to the row shown above with an identical layout except for it is in an N-Well region and the S/D diffusion is P+. Georgia Tech Microelectronics Research Center

    41. NMOS Inversion Gate Oxide Thickness (Å)Target = 300 Å Full Scale  200 to 1000 Å Scale  Georgia Tech Microelectronics Research Center

    42. NMOS Inversion Gate Oxide Thickness Summary Mean = 320 Å Target = 300 Å Average % Pass = 37% The mean of all the wafer medians is 320 Å, excluding the wafers with values in red. Using a LCL = 200 Å and UCL = 400 Å, the average % of good die for a given wafer is 37%, not excluding any wafers. Georgia Tech Microelectronics Research Center

    43. PMOS Inversion Gate Oxide Thickness (Å)Target = 300 Å Full Scale  200 to 1000 Å Scale  Georgia Tech Microelectronics Research Center

    44. PMOS Inversion Gate Oxide Thickness Summary Mean = 304 Å Target = 300 Å Average % Pass = 22% The mean of all the wafer medians is 304 Å, excluding the wafers with values in red. Using a LCL = 200 Å and UCL = 400 Å, the average % of good die for a given wafer is 22%, not excluding any wafers. Georgia Tech Microelectronics Research Center

    45. N and P-Well Accumulation Field Oxide Thickness (Å)Target = 6500 Å 6500 Å Target P-Well  6500 Å Target N-Well  Georgia Tech Microelectronics Research Center

    46. N-Well Accumulation Field Oxide Thickness Summary Mean = 2689Å Target = 6500 Å Average % Pass = 2% The mean of all the wafer medians is 2689 Å, excluding the wafers with values in red. Using a LCL = 5500 Å and UCL = 7500 Å, the average % of good die for a given wafer is 2%, not excluding any wafers. Georgia Tech Microelectronics Research Center

    47. P-Well Accumulation Field Oxide Thickness Summary Mean = 3173Å Target = 6500 Å Average % Pass = 6% The mean of all the wafer medians is 3173 Å, excluding the wafers with values in red. Using a LCL = 5500 Å and UCL = 7500 Å, the average % of good die for a given wafer is 6%, not excluding any wafers. Georgia Tech Microelectronics Research Center

    48. Transistor Structure 3 5 7 9 1 8 10 2 4 6 All NMOS & PMOS transistors have the same basic layout as above for W= 5, 10, & 50 um. Each row contains a unique L. Shown above is L = 25m. The variations of L are 1, 1.3, 1.5, 2, 3, 5, 10, 25 m. So there are 2 (NMOS/PMOS) x 8(various L) = 16 rows. In each row there are 3 transistors, so there are 3 x 16 = 48 unique transistors. Georgia Tech Microelectronics Research Center

    49. NMOS & PMOS Threshold Voltage (V)W=5 m, L=varying* *For each wafer L varies from left to right in the following order: 1, 1.3, 1.5, 2, 3, 5, 10, 25 m. Georgia Tech Microelectronics Research Center

    50. NMOS & PMOS Threshold Voltage (V)W=10 m, L=varying* *For each wafer L varies from left to right in the following order: 1, 1.3, 1.5, 2, 3, 5, 10, 25 m. Georgia Tech Microelectronics Research Center