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Power and a New Class of Future FPGA Architectures

Power and a New Class of Future FPGA Architectures

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Power and a New Class of Future FPGA Architectures

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  1. Power and a New Class of Future FPGA Architectures Sinan Kaptanoglu Actel, Fellow

  2. A Rough Outline • A historical look at FPGAs • A new market driver? • Future Technologies • Future Design Methods • Future Architectures Sinan Kaptanoglu, Actel Corp.

  3. A Historical Look at FPGAs Sinan Kaptanoglu, Actel Corp.

  4. Infancy (1985-1990) • FPGAs were invented in the 1985-1987 time frame. • Other programmable logic (PALs and PLDs) predate FPGAs by several years. • Infancy period is marked by: • Immature architectures and SW. • Too small, too slow, and too expensive for anything other than glue logic. Sinan Kaptanoglu, Actel Corp.

  5. Childhood (1990-1994) • Very exciting and inventive years. • Many startups, many new architectures. • PLDs grew into CPLDs and temporarily challenged the FPGAs. • FPGAs grew bigger, faster and cheaper. • Software became much better. • Synthesis replaced schematic capture. Sinan Kaptanoglu, Actel Corp.

  6. But… • By and large, FPGAs were still limited to doing glue logic. • For most applications, FPGAs were still not big enough, fast enough, or easy enough to design with. • The IC industry was driven by the PCs, in which FPGAs played no role at all. • In 1993, it looked like the entrenched ASICs would not budge at all. Sinan Kaptanoglu, Actel Corp.

  7. Then something new came… • Something that profoundly changed the FPGA landscape. • It was NOT a fantastic new FPGA architecture… • It was NOT a great and totally unexpected breakthrough in technology. Sinan Kaptanoglu, Actel Corp.

  8. It was a new market for FPGAs • “The Internet Age” had begun. • The rapidly growing datacom/telecom markets valued design flexibility and quick time-to-market more than cost or performance. • Suddenly, everybody needed bigger and faster routers and base infrastructure. • Development cycles for datacom were shrunk to mere months. • The volumes were low (not in millions). Sinan Kaptanoglu, Actel Corp.

  9. Datacom/telecom and FPGAs • FPGAs and datacom/telecom ideally suited each other, and they mutually drove each other’s boom: • FPGAs provided the needed flexibility and made new datacom/telecom products possible in short development cycles. • Datacom/telecom rapidly increased the FPGA revenues, starting a boom. • New applications ignited a rapid increase in the density and performance of FPGAs. Sinan Kaptanoglu, Actel Corp.

  10. The young adult years (1995-2001) • The datacom/telecom markets grew very rapidly, and their share of the programmable market grew with it. • Communication’s share was less than 10% in 1994. • It peaked out at 58% by 2000. • New architectures were developed and refined to better serve this market. • FPGA vendors had a great ally: Moore’s law and the ever shrinking process technology! • This allowed FPGAs to keep up with the needs of datacom by doubling the density every two years. • FPGAs became the next generation process drivers in the process foundries. Sinan Kaptanoglu, Actel Corp.

  11. Changing landscape… • Many startups died in this period. • FPGAs which were not targeted to datacom fell behind in revenue: • Anti-fuses were not reprogrammable and not well suited to datacom. This pushed Actel into other less lucrative markets. • Altera was flying high early, but it was in trouble by late 1990s, because CPLDs could not keep up with the increasing density of the FPGAs and the needs of the newer datacom applications. Sinan Kaptanoglu, Actel Corp.

  12. Then came the bust in 2001… • The communications industry felt the bust harder than any other sector. • Countless datacom/telecom start-ups went out of business. • Demand for new datacom/telecom equipment nose-dived. • In parallel, FPGA revenues declined 40% within a single year. • And the middle ages started. Sinan Kaptanoglu, Actel Corp.

  13. In the middle ages… • Xilinx kept designing FPGAs for the datacom/telecom market first and foremost. • Virtex was followed by: Virtex-2,4,5… • But they also developed lower cost derivatives for other markets. • Revenues declined initially, but they gradually recovered. • An era of slower growth began. Sinan Kaptanoglu, Actel Corp.

  14. In the middle ages… • Altera made a successful transition from CPLDs to FPGAs starting with Stratix and its derivatives. • Ironically, Stratix was aimed at the data-com market of the boom years. • Other markets were addressed with derivative lower cost products. • Like Xilinx’s, Altera’s revenues also declined initially, but gradually recovered. Sinan Kaptanoglu, Actel Corp.

  15. In the middle ages… • Actel successfully transitioned itself from making only anti-fuse FPGAs to flash based reprogrammable FPGAs. • These new devices were aimed at the low cost markets as well as markets that put a premium on design security. • Revenues declined initially, but recovered quickly. Sinan Kaptanoglu, Actel Corp.

  16. Middle ages (2002-2008) • FPGAs have settled down to a pattern of healthy but slower growth, with small ups and downs. • Market leading FPGAs continue being designed for datacom, but their low cost derivatives target all other markets combined. • FPGAs no longer appear to be a very vibrant industry with a lot of rapid innovation. • That’s the price one pays for maturity? • Take comfort: the ASICs are worse off. • Dataquest estimates that ASICs shrunk by 4% in 2007. Sinan Kaptanoglu, Actel Corp.

  17. Which future awaits FPGAs? • More of the same FPGAs? • Similar architectures for everybody? • Less innovation, more marketing? • Good continued growth, but at a slower pace… OR • Another boom: but what might start it? • If history repeats, it will be a rapidly growing new market for FPGAs! Sinan Kaptanoglu, Actel Corp.

  18. A new market driver? Sinan Kaptanoglu, Actel Corp.

  19. A new rapidly growing market • We are witnessing a dramatic increase in portable devices. • These are usually battery operated. • Not a temporary blip: • More new devices and types of devices are coming to market continuously. • Expected to accelerate in the 2010s. Sinan Kaptanoglu, Actel Corp.

  20. Consumer Industrial, Medical Military, Automotive Features Spectrum of portable devices Volume Sinan Kaptanoglu, Actel Corp.

  21. Portable market predictions • Gartner-Dataquest predicts 1.6B smart phones by 2010. • Juniper Research predicts 56M high end MP3 players by 2010. • Industrial/Medical/Automotive sectors are growing more rapidly than any other FPGA market. • Portable devices within these sectors are growing the fastest. Sinan Kaptanoglu, Actel Corp.

  22. Gartner-Dataquest estimates 2002 Market - $2.3B 2010 Market - $6.8B Mil/Aero Auto 6.9% Auto 0.6% Mil/Aero 6.2% Consumer 9.3% 7.6% Industrial Comm 15.3% 37.4% Comm Consumer 53.8% 14.6% Data Proc 15.7% New adopters are mostly from the consumer and the industrial sectors Industrial Data Proc 24.2% 8.2% Sinan Kaptanoglu, Actel Corp.

  23. What’s the big deal about the portable market? • Possibly there is no big deal: • Perhaps these are just yet another type of devices which may use FPGAs sometimes. • But we could have said the same thing about the datacom market back in 1993. • What similarities are there between the datacom market in 1993 and the portable device market in 2007? Sinan Kaptanoglu, Actel Corp.

  24. Similarities are… • In 1993, datacom had very short design cycles and preferred FPGAs. • But it could not use FPGAs frequently because the FPGAs often failed to meet minimum performance and density requirements. • In 2007, portable device market has short design cycles and prefer FPGAs. • But it cannot use FPGAs frequently because the FPGAs often fail to meet the minimum static power requirements. Sinan Kaptanoglu, Actel Corp.

  25. This market is different… • Because: • Most portables are battery powered. • Portable devices spend most of their time awake, idle, but doing very little. • Varies from 50% to 99.99% of the life. • This requires very low static power usage. • Compare that to datacom: • An FPGA in a router is active all the time. • Idle is for repairs and updates only. • A good FPGA for datacom is unlikely to be well suited for portables and vice versa. Sinan Kaptanoglu, Actel Corp.

  26. Don’t the low-cost derivatives address this market? • The low cost derivatives of market leading FPGAs indeed save area and power both. • But the static power of these devices are still two to three orders of magnitude too large for most battery powered applications. Sinan Kaptanoglu, Actel Corp.

  27. The minimum requirements: • The FPGAs for portable devices need a very low power “Idle” state. • Measured in tens of mW. • Idle state does not mean “switched off” or even deep “stand-by”: • Idle means very light activity. • Idle means that all FPGA flip-flops retain their state without being saved to and restored from a memory. • Switching from idle to active must be very quick in a few clock cycles, not thousands. Sinan Kaptanoglu, Actel Corp.

  28. Can this be done? Sinan Kaptanoglu, Actel Corp.

  29. An optimist’s view… • If we design new FPGA architectures custom tailored for the unique needs of the Portable device market, we give ourselves the best chance to witness a second boom in FPGAs. • These new FPGAs will not replace today’s products. They will co-exist with them to serve different markets. Sinan Kaptanoglu, Actel Corp.

  30. A pessimist’s view… • Most ICs don’t experience any boom. FPGAs were lucky to have had one! • We are unlikely to meet the idle power requirements of the portable market very soon. Therefore: • Accept maturity, and be happy with the slower but steady growth. Sinan Kaptanoglu, Actel Corp.

  31. OK, let’s be optimists for a while… How do we design FPGAs for the portable market? Sinan Kaptanoglu, Actel Corp.

  32. First learn from ASICs… • Use all the circuit and process tricks that the low-power ASICs have employed: • For the lowest leakage power, start by using a designated “low power” process from your favorite FAB. • Use high-k dielectrics for the gate, if available. Sinan Kaptanoglu, Actel Corp.

  33. Learn from ASICs: • Use a multiple-VT process. • Use highest VT devices wherever you can without adversely affecting performance. • For example, all configuration bits in an SRAM based FPGA should be built out of highest VT transistors. Sinan Kaptanoglu, Actel Corp.

  34. More tricks from ASICs… • Consider using a multi-Vdd process. • There has been a wealth of research on multi-VT and multi-Vdd circuit design for power reduction in ASICs. • If a multi-Vdd process is not available, consider using a reduced Vdd operation. • Consider using long-channel devices. • Consider power gating. Sinan Kaptanoglu, Actel Corp.

  35. More tricks from ASICs… • Consider using a triple-oxide-process, if available: • Good for gate leakage. • Extra mask, extra cost. • If available, use a triple-well process to take advantage of well biasing. • Again good for leakage, but costly. Sinan Kaptanoglu, Actel Corp.

  36. And yet more… • If you are really desperate, as a last resort, consider stacked gates. • Very costly (in area) for incommensurate returns in leakage reduction. Sinan Kaptanoglu, Actel Corp.

  37. And then, get help from SW… • Use all power-driven synthesis, tech-mapping, and place & route. • If you used well-biasing, or multiple VT, or multiple Vdd, let place & route arrange it as best as it can (in different parts of the FPGA) for the best power. • At the end, do power based bit-mask selection for configuration bits. Sinan Kaptanoglu, Actel Corp.

  38. When you have adopted most of these tricks from ASICs… • You have far exceeded the level of “low power” derivatives of the current popular FPGA architectures. • You have definitely improved static power, but not sufficiently. • You kept the changes to a minimum so that you can amortize the development effort for the original architectures. Sinan Kaptanoglu, Actel Corp.

  39. This is good, but not enough… • We need to explore fancier process technologies, circuit design methods and FPGA architectures. • The new FPGAs must be fully custom tailored for the portable market. • Even if that means they will not be very good for datacom applications. Sinan Kaptanoglu, Actel Corp.

  40. Promising technologies for FPGAs specifically targeted to portable devices Sinan Kaptanoglu, Actel Corp.

  41. The trend is not good… • CMOS process and portable devices seem to be heading in opposite directions. • The transistor leakage has increased with every CMOS shrink to date. • For source-drain and gate leakage both. • As we move down the silicon dimensions the leakage will only get worse. • It’s just physics. • Using the exact same type of materials, a shrink will leak more than the previous generation, unless the voltage is scaled. Sinan Kaptanoglu, Actel Corp.

  42. Vdd is not scaling! • Most 130nm low-power CMOS processes use 1.2V core operation. • So do most 90nm and 65nm low-power CMOS processes. • Most 45nm low-power processes will use 1.0V, or 0.9V at best. • Even those which use high-k dielectric materials. Sinan Kaptanoglu, Actel Corp.

  43. This is not very likely to change • Vdd will not scale very much in order to maintain a modest performance and in order to keep the gate leakage under control. • With or without high-k materials. • But the source-drain leakage will keep increasing from each process node to the next. Sinan Kaptanoglu, Actel Corp.

  44. Future technologies Three examples of promising technologies for future FPGAs for the portable device market Sinan Kaptanoglu, Actel Corp.

  45. Here is an incomplete list… • In increasing order of maturity: • SOIAS (Silicon-on-Insulator-with-an-Active-Substrate) technology. • Very high-k gate-oxide technology, with very small gate leakage. • Embedded flash-switch technology. • It is possible to combine any two or even all three. Sinan Kaptanoglu, Actel Corp.

  46. SIOAS technology Sinan Kaptanoglu, Actel Corp.

  47. Metal-1 bulk-SiO2Metal-1 gate (poly/metal) gate oxide n+ p- n+ Insulator (Si02) SOIAS based architectures • Let’s start first with the basic SOI: Sinan Kaptanoglu, Actel Corp.

  48. Metal-1 bulk-SiO2Metal-1 gate (poly/metal) gate oxide n+ p- n+ Insulator (Si02) p+ i-poly Insulator (Si02) SOIAS adds a back-substrate • From Yang et al. (1995, IEEE-IEDM) Sinan Kaptanoglu, Actel Corp.

  49. Fine-grain dynamic back-gate biasing • Fine grain back-bias: • In space and time both. • We can back bias individual logic modules, FFs or individual routing buffers. • Change biasing frequently. • Order of magnitude reduction in static power compared to low-power bulk-CMOS. • Need a highly sophisticated power driven synthesis, place and route. • Even ASICs can’t do this very well yet. Sinan Kaptanoglu, Actel Corp.

  50. SOI uses less dynamic power • Dynamic power is lower for any SOI due to lower gate and junction capacitances. • Many standard cell designs claim 50% dynamic power reduction compared to bulk CMOS (SOITECH claim.) Sinan Kaptanoglu, Actel Corp.