The Future of FPGA Interconnect

1. The Future of FPGA Interconnect Getting the LUT-heads to work… Guy Lemieux The University of British Columbia Tuesday, December 8, 2009 FPT 2009 Workshop

2. Layman’s viewpoint • How do I explain FPGA interconnect to mom? • Imagine planning a city on a grid • Maximum of 100,000 people, “LUT-heads” • For every LUT-head, given two things • Home location • Work location (often multiple work locations…) • Problem: Getting the LUT-heads to work! • Design a fixed road network • Every LUT-head drives in own lane (no time-sharing or bus) • Very expensive, lots of infrastructure “logicfamily”

3. Layman’s viewpoint (2) • Problem, Version 2 • After 25yrs, every LUT-head changes home & work • LUT-head population may grow or shrink • Same road network must still be used • Can only ‘reconfigure lanes’ by changing road paint • Problem, Version 3 • Start over, assuming 1,000,000 LUT-heads • New issues when the problem scales? • Average trip length ? • Average number of lanes in road ?

4. Overview • What’s in FPGA interconnect? • Review of typical design • What are the main application areas? • Driving the future of interconnect design • What are the interconnect metrics? • Pushing the envelope, then becoming practical • Open research problems? • Driving the future of interconnect design

5. Overview • What’s in FPGA interconnect? • Review of typical design • What are the main application areas? • Driving the future of interconnect design • What are the interconnect metrics? • Pushing the envelope, then becoming practical • Open research problems? • Driving the future of interconnect design

6. Input connections C Block S Block Altera Stratix Interconnect CLB aka LAB

7. Input connections IIB: input interconnect block Altera Stratix Interconnect

8. Input connections, neighbours 1 C Block S Block Connections in CLB grow bigger

9. Input connections, neighbours 2 C Block S Block Connections in C Block grow bigger

10. Output connections, local C Block S Block Altera Stratix Interconnect Single-driver: LUT outputs must only feed muxes

11. Output connections, global C Block S Block extended toinclude LUToutputs Altera Stratix Interconnect Single-driver: LUT outputs must only feed muxes

12. Design considerations • Design of C Block / IIB • Selects LUT inputs • Overall function: ‘M’ choose ‘kN’ • M = 100..500 wires (H + V) • N = 8 .. 16 LUTs • k = 4..6 inputs/LUT

13. Design considerations • Design of S Block • Steers M signals throughout array (turns) • Also accepts N LUT outputs • Topologically simple • Fs = 3: each wire connects to only 3 outgoing wires • Exception: LUT outputs connect to > 3 wires • Strongly influenced by circuit implementation • Bidirectional vs directional

14. Bidirectional vs. Directional Wiring bidir/dir == S Block Design + single-driver == C Block Design

15. Bidirectional Wires C Block S Block Logic

16. Bidirectional Wires Problem Half of tristatebuffers leftunused Buffers +input muxes dominate interconnect area

17. Bidirectional vs Directional

18. Bidirectional vs Directional

19. Bidirectional vs Directional

20. Bidirectional vs Directional

21. Bidirectional Switch Block

22. Directional Switch Block

23. Bidirectional vs Directional Switch BlockDirectional half as manySwitch Elements Switch ElementSamequantityand type ofcircuit elements, twice the wiring

24. Quantization of Channel Width No “partial”switch elementswith < Q wires Bidirectional (Q=1) 4 Switch ElementsCh. Width = 4 * Q= 4 * 1 Directional (Q=2) 2 Switch ElementsCh. Width = 2 * Q= 2 * 2

25. S Blocks with Long Wires • Long wires, span L tiles • Example L = 3 • Changes Q Q = L for bidirectional Q = 2L for directional CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB 1 2 3

26. Building up Long WiresStart with One Switch Element CLB CLB CLB CLB Wire ends for straight connections.

27. Building up Long WiresConnect MUX Inputs CLB CLB CLB CLB Extend MUX inputs

28. Building up Long WiresConnect MUX Inputs CLB CLB CLB CLB TURN UP from wire-ends to mux

29. Building up Long WiresConnect MUX Inputs CLB CLB CLB CLB TURN DOWN from wire-ends to mux

30. Building up Long WiresAdd +2 More Wires (4 total) CLB CLB CLB CLB Add LONG WIRES, turning UP and DOWN.

31. Building up Long WiresAdd +2 More Wires (6 total) CLB CLB CLB CLB Add LONG WIRES, turning UP and DOWN

32. Building up Long WiresTwisting to Next Tile CLB CLB CLB CLB Add wire twisting

33. Full S Block with Long WiresUsing One L=3 Switch Element (Q = 2L = 6) CLB CLB CLB CLB

34. Scaling Channel WidthUsing L=3 Switch Element 1 Switch ElementChannel width = Q = 6 2 Switch ElementsChannel width = 2Q = 12 CLB CLB CLB CLB VERY IMPORTANT: Area growth is linear with channel width CLB CLB CLB CLB

35. Long Wires  Changes Quantum • Long wires, span L tiles • Example L = 3 Q = L for bidirectional Q = 2L for directional CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB 1 2 3

36. Multi-driver WiringLogic outputs usetristate buffers (C Block) S Block S Block C Block Directional & multi-driver wiring CLB

37. Single-driver WiringLogic outputs use muxes(S Block) S Block S Block New connectivityconstraint Directional & single-driver wiring CLB

38. Directional, Single-driver Benefits • Average improvements 0% channel width 9% delay 14% tile length of physical layout 25% transistor count 32% area-delay product 37% wiring capacitance • Any reason to use bidir? • Important implications on future interconnect!

39. C Block design C Block

40. C Block design M inputs (100 … 500) Up to kN outputs (4*8 ... 8*10)

41. C Block design

42. C Block design • Sparse crossbar • Similar # switchpoints • On inputs • On outputs • Spread out pattern • Two columns have maximum Hamming distance (most # of different switch points) • True for all pairs of columns

43. Overview • What’s in FPGA interconnect? • Review of typical design • What are the main application areas? • Driving the future of interconnect design • What are the interconnect metrics? • Pushing the envelope, then becoming practical • Open research problems? • Driving the future of interconnect design

44. What are the main application areas? • What are FPGAs used for? • A long long time ago… small glue logic • Modern… • Internet routers (table lookups, multiplexing) • Embedded systems design (NIOS II, MicroBlaze) • Cell phone basestations (communications DSP) • HDTV sets / set-top boxes (video/image DSP) • Future?

45. Application drivers • What we know • FPGAs increasingly more powerful, constant cost • ASIC design costs escalating wildly • Most ASICs use older technology (0.18/0.13mm) • Increasingly, ASICs implemented as FPGAs instead • FPGAs only in low-volume • E.g., being designed-out of HDTV sets • Extrapolate to find new emerging markets …

46. Application drivers (2) • Extrapolating… • Industrial/scientific instruments: low volume, high margin • Medical sensing, imaging (ultrasound, PET, …) • Electronics test & measurement (router tester, …) • Physics (neutrino detection, …) • Computation: mixed volume, mixed margin • Computer system simulation (RAMP, …) • Molecular dynamics, financial modeling, seismic / oil & gas • Portable/handheld: mixed volume, mixed margin • Consumer • Industrial/Medical

47. Application drivers (3) • Problems with FPGAs • Expensive for high-volume markets • Need cost-reduction strategy • Insufficient capacity • Could just wait for Moore’s Law to catch up • Capture emerging markets early: ultra-capacity FPGA • Hard to program • Particularly important when used for computation • Domain-specific languages help • Power • Slow

48. Overview • What’s in FPGA interconnect? • Review of typical design • What are the main application areas? • Driving the future of interconnect design • What are the interconnect metrics? • Pushing the envelope, then becoming practical • Open research problems? • Driving the future of interconnect design

49. Interconnect metrics • Typical • Area • Delay (latency) • Power • Obscure, but important! • Co$t • Bandwidth • Programmability/Ease of use • Reliability/Integrity • Flexibility/Runtime reconfigurability

50. Pushing the envelope • Research is about discovery, ideas, exploration • Also evaluation, limit studies, potential uses • One general research strategy • Pick a metric • Push the envelope • How far did you get? • Back off until practical • Re-integrate with reality