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Explore the complexities of advanced semiconductor design challenges such as manufacturability, design verification, variability modeling, and roadmap development. Delve into the intricacies of addressing these issues at various levels of abstraction to enhance design productivity and reduce variability. Understand the historical emphasis, capacity, robustness, and specialized methodologies required for effective design verification. Discover strategies for tackling challenges in both larger and smaller nanometer designs, including verification in the presence of non-digital effects and addressing soft failures in complex systems.
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ITRS Design
Design • Design for manufacturability • Design verification
Design for Manufacturability • Architecture challenges • Logic and circuit challenges • Layout and physical design challenges • Yield prediction and optimization
Variability Modeling and Roadmap – Need for Such a Roadmap • Expected to be the source of multiple DFM challenges • Invest in variability reduction or design productivity improvements?
Variability Modeling and Roadmap – Levels of Abstraction • Circuit/Chip level • Device level • Physical level
Design Verification • Verification vs testing • Moore’s law • Historical emphasis in design improvement
Design Verification – Challenges (>50nm) • Capacity • Robustness • Verification metrics • Software • Reuse • Specialized verification methodology • Specialized design-for-verifiability • New kinds of concurrency
Design Verification – Challenges (<50nm) • Design for verifiability • Higher levels of abstraction • Specification for verifiability • Verification in presence of non-digital effects • Heterogeneous systems • Analog-Mixed signal • Soft failures • Verification for redundancy