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Understanding ROMs, RAMs, PLDs & MPLDs in Digital Design Lecture

Learn about Read-Only Memories (ROM), Random-Access Memories (RAM), Programmable Logic Devices (PLDs), and Macrocell Logic in this comprehensive digital design lecture. Explore various configurations, programming tables, and examples to enhance your knowledge.

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Understanding ROMs, RAMs, PLDs & MPLDs in Digital Design Lecture

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  1. Digital DesignLecture 14 ROMs and RAMsMano, 7.6-7.8

  2. PLD Configurations

  3. An Example PLA • Buffers providetrue and complement ofinputs • XORs provideprogrammable complementors on outputs • Similar to PROM • Partial variabledecoding • Only someminterms

  4. PLA Programming Table Table 7-5

  5. Solution to Example 7-2 Implement F1(A,B,C)=(0,1,2,4) F2(A,B,C)=(0,5,6,7)

  6. Programmable Array Logic • Fixed OR array • ProgrammableAND array

  7. PAL Fuse Map PAL Programming Table Table 7-6

  8. Sequential PLDs

  9. Sequential Programmable Devices • Sequential (simple) programmable Logic device (SPLD) • Field-programmable logic sequence (FPLS, defunct – too hard to use) • Registered PAL / macrocell structure • Complex programmable logic device (CPLD) • Collection of SPLDs on a chip • Field programmable gate array (FPLA) • Logic blocks (look-up tables, multiplexers, gates, flip-flops) • Programmable input/output blocks • Programmable interconnections • Microprocessor (using PROM)

  10. Macrocell Logic

  11. CPLD

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