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Digital Design Lecture 10

Digital Design Lecture 10. Sequential Design. State Reduction. Equivalent Circuits Identical input sequence Identical output sequence Equivalent States Same input  same output Same input  same or equivalent next state. Next State x=0 x=1 a b c d a d e f a f

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Digital Design Lecture 10

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  1. Digital DesignLecture 10 Sequential Design

  2. State Reduction • Equivalent Circuits • Identical input sequence • Identical output sequence • Equivalent States • Same input  same output • Same input  same orequivalent next state

  3. Next Statex=0 x=1 a b c d a d e f a f g f a f Outputx=0 x=1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 • g & e equivalent, f & d equivalent State a b c d e f g

  4. State Assignment State a b c d e Binary 000 001 010 011 100 Gray Code 000 001 011 010 110 One-Hot 00001 00010 00100 01000 10000

  5. Reduced State Table:Binary State Assignment Next Statex=0 x=1 000 001 010 011 000 011 100 011 000 011 Outputx=0 x=1 0 0 0 0 0 0 0 1 0 1 State 001 010 011 100 101 Table 5-10

  6. Design Procedure • Develop State Diagram From Specs • Reduce States • Assign Binary values to States • Write Binary-coded State Table • Choose Flip-Flops • Derive Input and Output Equations • Draw the Logic Diagram

  7. Develop State Diagram:Sequence Detector • Detect 3 or more 1s in sequence(a Moore Model)

  8. D Flip-Flop Input Equations StateA B 0 00 00 10 11 01 01 11 1 Input x 0 1 0 10101 Next StateA B 0 00 10 01 00 01 10 01 1 Output y 0 0 0 00011 A(t+1) = DA(A,B,x) = (3,5,7) B(t+1) = DB(A,B,x) = (1,5,7) y(A,B,x) = (6,7) Input equations come directly from the next state in D Flip-Flop design

  9. Simplified Boolean Equations

  10. Sequence Detector: D Flip-Flops

  11. JK Flip-Flop T Flip-Flop Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 01XX K XX10 Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 T 0110 Using JK or T Flip-Flops 1. Develop Excitation Table Using Excitation Tables Table 5-12

  12. State Table: JK Flip-Flop Inputs PresentState Input NextState Flip-Flop Inputs A 00001111 B 00110011 x 00001111 A 00101110 B 01010110 JA 00101110 KA 01010110 JB 00101110 KB 01010110 Table 5-13

  13. Maps for J and K Input Equations

  14. JK Flip-Flop Sequence Detector

  15. Synthesis Using T Flip-Flops:Designing a Counter

  16. 3-Bit Counter State Table Present State Next State Flip-Flop Inputs A2 00001111 A1 00110011 A0 01010101 A2 00011110 A1 01100110 A0 10101010 TA2 00010001 TA1 01010111 TA0 11111111

  17. 3-Bit Counter Karnaugh Maps

  18. The 3-Bit Counter

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