HyperTransport™ Technology. INTRODUCTION. WHAT IS HYPER TRANSPORT TECHNOLOGY? CAUSES LEADING TO DEVELOPMENT OF HYPER TRANSPORT TECHNOLOGY. I/O bandwidth problem High pin count High power consumtion. The I/O Bandwidth Problem.
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High pin count
High power consumtion
Improve system performance
- Provide increased I/O bandwidth
- Ensure low latency responses
- Reduce power consumption
Simplify system design
- Use as few pins as possible to allow smaller packages and to reduce cost
Increase I/O flexibility
- Provide a modular bridge architecture
Maintain compatibility with legacy systems
- Complement standard external buses
- Have little or no impact on existing operating systems and drivers
Ensure extensibility to new system network architecture (SNA) buses
Provide highly scalable multiprocessing systems
HyperTransport technology creates a packet-based link implemented on two independent, unidirectional sets of signals. It provides a broad range of system topologies built with three generic device types:
- All 16-bit, 32-bit, and asymmetrically-sized configurations must be enabled by a software initialization step.
- After a cold reset BIOS reprograms all linked to the desired width