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MICE Data Flow

MICE Readout DFPGA F’ware Bowie K, Galagedera S, Halsall, Hart T, Kaplan D, Mellis M, Long K, Luebke W, C Macwaters, Rubinov P & Collaboration. MICE Data Flow. Tracker. AFE IIt board. TriP-t Pipeline. VLPC. ADC. AFPGA. C OLEC. DFPGA. Serdes. VLSB memory bank.

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MICE Data Flow

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  1. MICE ReadoutDFPGAF’ware Bowie K, Galagedera S, Halsall, Hart T, Kaplan D, Mellis M, Long K, Luebke W, C Macwaters, Rubinov P & Collaboration

  2. MICE Data Flow Tracker AFE IIt board TriP-t Pipeline VLPC ADC AFPGA C OLEC DFPGA Serdes VLSB memory bank

  3. Detailed AFEllt data flow 2 x

  4. Four DFPGAs/ AFEllt Four Interfaces 18 ns Clock period L1-Data readout 21 bit SERDES C o l l e c t o r Disc 0 map 16 bit Trip-t JTAG 3 bit DIGEN0[ U/L/B] Clock DFPGA 2 bit 3 bit Mode DIGEN3[ U/L/B] Busy Disc 3 map 16 bit D-A FPGA 11 bit (Disc bit map/ L1-Data readout) x 2 DFPGA Interfaces

  5. Trip-t Interface MapFIFO0UMSB MapFIFO0ULSB Disc 0 map 16 bit MapFIFO0LMSB MapFIFO0LLSB D-A FPGA Interface DIGEN0[ U/L/B] PRE-RST M U X Trip-t Interface MODE CTRL TxFIFO-D 8 bit 16 ->1 Read Select U/L Write DIGEN3[ U/L/B] MapFIFO3UMSB MapFIFO3ULSB Disc 3 map 16 bit MapFIFO3LMSB MapFIFO3LLSB

  6. Trip-t Interface Timing 162ns (9x18ns) 162ns (9x18ns) PRE-RST 18ns DIGENU 18ns DIGENL 18ns DIGENB

  7. 8 Bit Bi Directional Data 1 Write Enable (TxEF-D) from DFPGA to AFPGA. 1 Write Enable (TxEF-A) from AFPGA to DFPGA. 1 PRE_RST signal from AFPGA to DFPGA. RxEF-D RxEF-A A FPGA D FPGA RxFIFO-D Disc-Vshare 11 Bit RxFIFO-A TxFIFO-A TxEF-D TxEF-A Idle Data 1 Data 2 Data 3 Idle Data n Chk sum TxEF-AorD ‘1’ ‘0’ TxFIFO-D D-A FPGA Interface

  8. 21 Bit SerdesFIFO output interfaces to its own Serdes. Input to SerdesFIFO come from #2 off RxFIFO-Ds. Bit Allocation 0 1/7th clock signal 1 – 8 Bit 0 to 7 of RxFIFO-D L1-data from AFPGA1 9 AFPGA1 L1-data sub-event frame signal 10 Free 11 - 18 Bit 0 to 7 of RxFIFO-D L1-data from AFPGA2 19 AFPGA1 L1-data sub-event frame signal 20 L1-data event frame signal to cover both AFPGA1 & AFPGA2 SERDES Interface

  9. DFPGA code follow Run time commands issued by the grey coded 2 bit Collector mode command lines [mode 1:0]. One Busy flag from DFPGA to Collector. The four Collector modes are Idle mode [mode 0:0] -Lower Busy Active mode [mode 0:1] -Lower Busy Digitise mode [mode 1:1] -Raise Busy Readout mode [mode 1:0] -Lower Busy Next expected valid modes are either the Idle or Active. Collector Interface

  10. DFPGA Schematic (DF->AF single channel)

  11. Dynamic Simulation

  12. Dynamic Simulation- Data in

  13. Dynamic Simulation- Data Out

  14. Done 2xTrip-t  DFPGA  AFPGA (single channel) design simulated correctly with static data. 2xTrip-t  DFPGA  AFPGA (single channel) design simulated correctly with dynamic data. pins configured. 2xTrip-t  DFPGA  AFPGA(single channel) back annotated design simulated correctly with dynamic data. Max operating frequency 66 MHz Underway Communications interface Next Test Implement L1 Data Readout MICE Readout DFPGA Firmware Progress

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