html5-img
1 / 23

A Fully Integrated 4GHz Continuous-Time Bandpass Δ∑ Converter

A Fully Integrated 4GHz Continuous-Time Bandpass Δ∑ Converter. Q. Béraud-Sudreau , A. Mariano, D. Dallet, Y. Deval, J.B. Begueret IMS Laboratory - University of Bordeaux - France. Outline. Motivations Software Defined Radio (SDR) ADC Architecture BP ∆  Modulator Resonator Design

enid
Download Presentation

A Fully Integrated 4GHz Continuous-Time Bandpass Δ∑ Converter

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Fully Integrated 4GHz Continuous-Time Bandpass Δ∑ Converter Q. Béraud-Sudreau, A. Mariano, D. Dallet, Y. Deval, J.B. Begueret IMS Laboratory - University of Bordeaux - France

  2. Outline • Motivations • Software Defined Radio (SDR) • ADC Architecture • BP ∆ Modulator • Resonator Design • Resonator Architecture • Simulations • Expected performance • Conclusion

  3. ADCs in Digital Receivers: Towards the “Software Defined Radio” Trend  Eliminate Downconversion, simplify the system Advantages: – Digital robustness – Better Channel Matching – Frequency agility – More Degrees of Freedom Challenges: – ADC needs huge dynamic range – Enormous data reduction needed in DSP

  4. ADCs in Digital Receivers: Towards the “Software Defined Radio” Trend  Eliminate Downconversion Advantages: – Digital robustness – Better Channel Matching – Frequency agility – More Degrees of Freedom Challenges: – ADC needs huge dynamic range – Enormous data reduction needed in DSP CT Δ∑ ADC

  5. Continuous-Time Bandpass ∆ Converter ADC architecture for Digital Receivers – Elimination of downconversion stage – Improved I and Q matching – Improved performance with digital modulation schemes – Improved flexibility with communication standards

  6. Continuous-Time Bandpass ∆ Converter Digital Receiver Ultra-Fast IC technologies Challenges – High ADC sample rates required – High ADC dynamic range required Direct ConversiontowardsSoftware Defined Radio

  7. CT ∆ Modulator Architecture • DACs association (NRZ et HNRZ) • “Multi-feedback” architecture • Multi-bit quantizer • 4th order modulator Fin = Fs/4 NRZ: Non Return to Zero HNRZ: Half delayed NRZ

  8. CT ∆ Modulator Architecture • DACs association (NRZ et HNRZ) • “Multi-feedback” architecture • Multi-bit quantizer • 4th order modulator Output Spectrum Fin = Fs/4 Simulation Parameters Amplitude (dB) * OSR = Fs/2BW SNR = 87 dB @ 20MHz

  9. Continuous-time ∆ Converter Context Non-idealities • Need for high performance 2nd order filters • Quality factor impact the SNR and the bandwidth of the modulator  2nd order resonators

  10. Resonator Non-idealities • The resonators can be implemented using LC, Gm-C, RC or MEMS/SAW filters. • Integrated components have a low Q due to parasitic resistive losses • A Q enhancement circuit is needed. • Feedback loop  Desired noise-shaping • A transconductor will convert the voltage in current performance degradation

  11. Fourth-order BP  Modulator Topology Context Non-idealities Two 2nd order resonators • Based on transconductors (G), • Two 2nd order resonators (L,R,C and Qt), • A 3-bit quantizer, • D-latches, • Feedback DACs (NRZ and HNRZ).

  12. Resonator Architecture Non-idealities Transconductor (G) • Fully differential structure • Common mode rejection • Cascode topology • Increase the bandwidth • Higher output resistor • Degenerated common source • Provide good linearity

  13. Resonator Architecture Non-idealities Resonator • Fully differential structure • Cross-coupled LC-tank topology

  14. Resonator Architecture Non-idealities Resonator • Fully differential structure • Cross-coupled LC-tank topology • LC tank

  15. Resonator Architecture Non-idealities Resonator • Fully differential structure • Cross-coupled LC-tank topology • LC tank • Q-enhancement circuit

  16. Resonator Architecture Non-idealities Resonator • Obtained quality factor for the 4th order filter (both resonators chained): Q= 630

  17. Mixed Simulations Transistor-level Circuit VHDL-AMS Modeling Frequency (Hz) SNR = 70 dB @ 20MHz

  18. Mixed Simulations Transistor-level Circuit VHDL-AMS Modeling Frequency (Hz) SNR = 68 dB @ 30MHz

  19. Schematic

  20. DACs CT ∆ ADC Layout resonators Quantizer & DFF Clock buffer LVDS Buffer

  21. Post Layout Simulation Obtained output spectrum SNR = 67 dB @ 30MHz

  22. Conclusion • Modeling and circuit design • 2nd order resonators CT BP Δ Modulators • Mixed simulation • Overall CT BP Δ Modulator • Validate the resonators circuit design • Post Layout Simulation • Validate the ADC circuit design

  23. Thank you for your attention! quentin.beraud-sudreau@ims-bordeaux.fr

More Related