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Designing with MAX+PLUS II

Designing with MAX+PLUS II. Class Agenda. MAX+PLUS II Design Environment MAX+PLUS II Design Methodology Design Entry Compilation Simulation Timing Analysis Device Programming Review and Support. MAX+PLUS II Design Environment. MAX+PLUS II IS. A fully integrated CPLD development system

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Designing with MAX+PLUS II

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  1. Designing with MAX+PLUS II

  2. Class Agenda • MAX+PLUS II Design Environment • MAX+PLUS II Design Methodology • Design Entry • Compilation • Simulation • Timing Analysis • Device Programming • Review and Support

  3. MAX+PLUS IIDesign Environment

  4. MAX+PLUS II IS... • A fully integrated CPLD development system • Provides an architecture-independent design environment • Supports ALL Altera devices (one Library for all devices) • Supports broad range of design needs • Design Entry • Synthesis • Place & Route (fitting) • Simulation • Timing Analysis • Device Programming • Provides extensive on-line help • Supports multiple platforms ( PC, Workstation ) • Supports multiple EDA vendors and standards

  5. MAX+PLUS II Can... Design Entry Design Compilation Verification & Programming EDIF Verilog VHDL SDF Standard EDA Design Entry: Standard EDA Design Verification: EDIF LPM Others Cadence Mentor Graphics OrCAD Synopsys Viewlogic Others Cadence Mentor Graphics Logic Modelling Synopsys Viewlogic Others MAX+PLUS II Compiler Design-Rule Checking Graphic Design Entry Timing Simulation Logic Synthesis & Fitting Text Design Entry (AHDL, VHDL, Verilog HDL) Functional Simulation Multi-Device Partitioning Waveform Design Entry Multi-Device Simulation Automatic Error Location Hierachical Design Entry Timing Analysis Timing-Driven Compilation Floorplan Editing Device Programming • Operate in a self-contained environment

  6. Or... MAX+PLUS II • Operate seamlessly with other EDA tools Altera Gate Array Conversion Kit LMF TDF Verilog HDL & VHDL Design Files MAX FLEX Classic Standard EDA HDL Files EDIF Standard EDA Schematics Verilog HDL VHDL EDIF SDF Standard EDA Simulator

  7. MAX+PLUS II Operating Environment • MAX+PLUS II Manager • Start-up window Toolbar provides shortcuts for commonly used functions Project Directory and Project name MAX+PLUS II menu gives you access to all MAX+PLUS II functions Help menu gives you access to on-line help Status bar provides a brief description of selected menu command and toolbar button

  8. Questions about MAX+PLUS II? • MAX+PLUS II On-Line Help has the answers • Contains the complete up-to-date information on MAX+PLUS II • Provides tips on how to effectively work with MAX+PLUS II tools • Provides answers and examples • Digital Library CD-ROM

  9. MAX+PLUS IIDesign Methodology

  10. Design Entry Design Modification Design Specification Design Compilation Functional Verification Timing Verification Device Programming In-System Verification System Production

  11. Design Entry • Multiple design entry methods • MAX+PLUS II • Graphic design entry • Text design entry • AHDL, VHDL • 3rd party EDA tools • EDIF • FPGA-Express • OrCAD schematics, Xilinx (XNF) files • Files can be mixed and matched in a hierachical project • Use LPM and Megafunctions to accelerate design entry • Megawizard is an easy to use interface

  12. Design Entry Files MAX+PLUS II Symbol Editor MAX+PLUS II Floorplan Editor Top-Level File VHDL/Verilog OrCAD MAX+PLUS II Graphic Editor MAX+PLUS II Text Editor AHDL Top-level design files can be .gdf, .tdf, .vhd, .sch, or .edf Synopsys, ViewLogic, Mentor Graphics, etc... Waveform .gdf .wdf .tdf .vhd .sch .edf .xnf Graphic File Waveform File Text File Text File Graphic File Text File Text File Schematic Xilinx Generated within MAX+PLUS II Imported from other EDA tools

  13. Graphic Design Entry • Set up a new project • Draw schematic • Enter symbols • Connect wires • Type in signal names • Save and check the design • The file extension is .gdf • Correct any errors with the aid of Message Processor • Create symbol or include file

  14. Set Up A New Project • Every design must have a project name • Project name must match design file name Project Name Project Directory

  15. Open New File & Enter Symbols • Open a new .gdf file in Graphic Editor • Double click in Graphic file to enter symbol Open new file Double click in Graphic Editor Type in symbol name or click on symbol name Symbol libraries Symbols in the selected library

  16. Available Libraries • prim ( Altera primitives ) • Basic logic building blocks • mf ( Macrofunction ) • 7400 family logic • mega_lpm ( LPMs, Megafunctions and MegaCores ) • Library of Parameterized Modules ( LPMs ) • High-level building blocks • Megafunctions are high level function module • busmux, csdpram, csfifo, parallel_add, etc... • MegaCores are IP models you can try before purchase • UARTs, FFT, etc… • AMPP ( Altera Megafunction Partners Program ) • Partners providing PCI, DSP, uControllers, etc...

  17. Using LPM & Megafunctions • Select ports • Set parameters Click on the Help button to get information about the LPM or Megafunction Set desired ports by clicking on Port Name and set Port Status to Used or Unused Set desired parameters by clicking on Parameter Name and set the desired value in the Parameter Value field

  18. Add User Libraries • Access user created libraries • Add user library directories • Set priorities Select the library directory then click on Add Library search priority can be changed. The Project directory has the highest priority, followed by the User Libraries, then by the Altera Libraries

  19. Making Connections • Wire • Single bit line • Bus • Multi-bit line • Signal name • Matching name • Attached to wire Bus - Bus signal names required for LPM module buses Wire Drawing tool shortcuts Wire to Bus Connection

  20. Graphic Editor Options • Font, Text Size • Text Control • Line Style • Select Wire or Bus • Display Assignments • Turns display on or off • Guideline Control • Controls grid lines • Rubberbanding • Wires move with symbols

  21. Save & Check the Design • Save & check the design file with .gdf extension • Correct any errors with the aid of Message Processor Design File Name Project Directory

  22. Message Processor • Lists all Info, Warning and Error messages • Info messages are general information • Warning messages are possible problems • Error messages indicate Compiler is unable to complete compilation process • Provides help on the messages • Locates source of message in design file Messages Information about message Go to next or previous message Locate source in design file

  23. Generate Symbols and Include Files • Create symbol for higher-level schematic capture • Create include file for AHDL function prototype Create symbol Create include file

  24. Symbol Editor • Symbols can be modified with the Symbol Editor

  25. Example Section (LAB 1)

  26. Demo 1 (Basic Graphic design Entry) Design flow of the circuit Print out

  27. Demo 2 (1) Draw the following circuit (2) Use the Save & Check Option (3) Use the Error Message to Locate the Error (4) Correct the Error

  28. Demo 2 (use Save & Check Option) Build the following circuit from the provided library VHDL LPM GDF Viewlogic EDIF Sel[1..0] AHDL

  29. Text Design Entry • Set up a new project • Same as Graphic Design Entry • Enter text description • AHDL • VHDL • Save & check the design • Similar to Graphic Design Entry • The file extension is .tdf or .vhd

  30. AHDL • Altera Hardware Description Language • High-level hardware behavior description language • Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. • Especially well-suited for large or complex state machines • All described behavior is implemented concurrently • Use Insert AHDL Template in the Text Editor Learn more about AHDL in the customer training class: Designing with MAX+plus II Using AHDL

  31. VHDL • VHSIC Hardware Description Language • IEEE standard • High-level hardware behavior description language • Especially well-suited for large or complex designs • Use Insert VHDL Template in the Text Editor Learn more about VHDL in the customer training class: Designing with MAX+plus II Using VHDL

  32. Imported Design • Top-level Design • Some top-level designs can be read directly by the compiler • EDIF Netlist files • VHDL Netlist files • Xilinx Netlist files • Save top-level OrCAD schematics as .gdf file in Graphic Editor • Subdesigns (lower level modules) • EDIF, VHDL, OrCAD schematics, Xilinx files • Create symbols and include files • Embed symbols or include files in Graphic or Text Editor • Other proprietary files • JEDEC, ABEL, PALASM • Conversion ultilities exist in Altera ftp site

  33. MAX+PLUS II Hierachy Display • Displays current design files as a hierachy tree • Traverse the hierachy tree with ease • Displays all files associated with the current project • Open and close files directly ( click on right button of mouse )

  34. Design Entry Recommendations • Use LPM/Megafunction whenever possible • Use hierarachical design methodology • Use Hierarachy Display for fast access to design file at any level • Use Message Processor to locate source of error in design file

  35. Design Entry Summary MAX+PLUS II Symbol Editor MAX+PLUS II Waveform Editor .gdf .wdf .sym MAX+PLUS II Graphic Editor MAX+PLUS II Text Editor .tdf .vhd .inc .sch .edf .lmf .xnf Design Files Support Files MAX+PLUS II User 3rd Party EDA Tools

  36. Compilation Design Entry Design Modification Design Specification Simulation Timing Analysis Device Programming In-System Verification System Production

  37. MAX+PLUS II Compiler • Process all design files associated with the project • Files can be created with MAX+PLUS II or 3rd party EDA Tools • Checks for syntax errors and common design pitfalls • Performs logic synthesis and place & route • According to assignments in .acf file • Generates files for simulation and timing analysis • Files can be used by MAX+PLUS II or 3rd party EDA Tools • Generates files for programming targeted devices

  38. Compiling a Project • Assign target device • Set logic synthesis controls • Set place & route controls • Select functional compilation or timing compilation • Run the compilation • Consult the report file (.rpt) or the Floorplan Editor for device utilization summaries and synthesis and place & route results

  39. Compiler Input and Output Files 3rd Party EDA Design Files (.edf, .sch, .xnf) Mapping Files (.lmf) Functional SNF Files (.snf) MAX+PLUS II Compiler MAX+PLUS II Design Files (.gdf, .tdf, .vhd) Compiler Netlist Extractor (includes all netlist readers Database Builder Logic Synthesizer Timing SNF Files (.snf) Functional, Timing, or Linked SNF Extractor Partitioner Fitter Assignments (.acf) EDIF, VHDL & Verilog Netlist Writers Design Doctor Assembler Programming Files (.pof, .sof, .jed) 3rd Party EDA Simulation/Timing Files (.edo, vo, vho, sdo)

  40. Compiler Input Files • Design files • MAX+PLUS II • Graphics file (.gdf), AHDL file (.tdf), VHDL file (.vhd) • 3rd Party EDA Tools • EDIF file (.edf) • Select Vendor in EDIF Netlist Reader Settings • Library Mapping File (.lmf) required for vendors not listed • OrCAD file (.sch), Xilinx file (.xnf) • Assignment and Configuration File (.acf) • Controls the Compiler’s synthesis and place & route operations • Automatically generated when user enter assignments • Automatically updated when user changes assignments or backannotes project

  41. Compiler Output Files • Design verification files • MAX+PLUS II • Simulation Netlist File (.snf) • 3rd Party EDA Tools • VHDL netlist file (.vho) • EDIF netlist file (.edo) • Verilog netlist file (.vo) • Standard Delay Format SDF file (.sdo) • Programming files • Programmer Object file (.pof) • SRAM Object file (.sof) • JEDEC file (.jed)

  42. Assignments • Assignments are used to control logic synthesis and place & route operations • Assignments are generally made after the compilation process to resolve fit or performance issues • Examples of assignments are: • Device assignment • Synthesis Logic Options • Timing Requirements • Pin/Location/Chip • Clique • Assignments are stored in the .acf file

  43. Making Device Assignment • Select Device • Specific device • Auto • MAX+PLUS II chooses smallest and fastest device the design fits into Select device Family Auto device selection Specific device selection

  44. Controlling Logic Synthesis • The logic synthesis operation is a trade-off between area, speed, and ease-of-fit • MAX+PLUS II gives users the control • Two levels of controlling logic synthesis: • Individual logic level • Localized effect • Affects only the selected nodes, pins and logic blocks • Global logic level • Global effect • Affects all nodes, pins and logic blocks • Recommendation: use the logic synthesis controls only after design analysis of first compilation

  45. Individual Logic Level Control • Highlight node, pin or logic block • Choose Assign menu then Logic Options • Two ways of making individual logic level assignment: • Individual Logic Options assignment • Synthesis Styles assignment

  46. Individual Logic Option Assignment • Provides controls to turn individual architectural features and synthesis algorithms on or off Gray or Default (default): set by higher level or global setting Check or Auto: enable feature Blank or Ignore: disable feature

  47. Synthesis Style Assignment • Predefined frequently used groups of logic options • None (default): set by higher level or global setting • FAST: enable features • NORMAL: disable features • WYSIWYG: implement design as is • User can customize own styles

  48. Global Logic Level Control • Choose Assign then Global Project Logic Synthesis • Select from predefined synthesis style • NORMAL (default), FAST or WYSIWYG • Or create user taylored settings

  49. More Methods of Controlling Synthesis Making Timing Requirements assignment (FLEX devices only) • Specifies desired speed performance • Use after performing timing analysis to improve specific timing path • Localized control • Highlight Pin • Choose Assign then Timing Requirements • Assign desired tpd, tco, tsu, fmax values • Global control • Chosse Assign then Global Project Timing Requirements • Assign desired tpd, tco, tsu, fmax values

  50. Controlling Place & Route • Recommendation: Give MAX+PLUS II the freedom to place pins and logic cells • Do not make Pin/Location/Chip assignments unless absolutely necessary • Use Pin/Location/Chip assignments to solve specific performance/fit problems found in design analysis • If needed, Pin/Location/Chip assignments can be made from design source file or the Floorplan Editor • Assignments can only be made to “hard” nodes or lower-level designs that contains hard nodes • Hard nodes are objects that translates directly into objects in silicon e.g. flipflop, LCELL and I/O pins

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