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EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm

EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm. May 7, 2009 Richard Dorrance & Newton Hang. Motivation. Reduce power dissipation Subthreshold logic as alternative to CMOS Improve full adder design Low power arithmetic and computation Increase robustness in subthreshold logic

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EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm

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  1. EE241 Spring 2009:Robust Subthreshold Adder Design in 32nm May 7, 2009 Richard Dorrance & Newton Hang

  2. EE241 Spring 2009 Motivation • Reduce power dissipation • Subthreshold logic as alternative to CMOS • Improve full adder design • Low power arithmetic and computation • Increase robustness in subthreshold logic • Make subthreshold 32nm full adder feasible

  3. EE241 Spring 2009 Current and Proposed Techniques • Sizing • Super-threshold sizing ratio not optimal in subthreshold • Up size transistors x3-10 for increased robustness • Sub-DTMOS • “Dynamic Body-Biasing” • Reduced Threshold Voltage & Increased Mobility (Subthreshold slope approaches 60 mV/dec)

  4. EE241 Spring 2009 1-Bit Full Adder Cells

  5. EE241 Spring 2009 Experimental Setup • 250 Monte Carlo Simulations • All 56 input transitions tested • Sum & Carry Noise Margins • Worst case delay to Sum & Carry • Average Power • 100 Monte Carlo Simulations • 50 random test vectors • Functionality (99.99% certainty) • Worst case delay to Sum & Carry • Average Power

  6. EE241 Spring 2009 Noise Margins: Sum

  7. EE241 Spring 2009 Noise Margins: Carry

  8. EE241 Spring 2009 Failure Rates in N-Bit Ripple Carry Adders

  9. EE241 Spring 2009 • Reasons for Failure • Lack of individual cell robustness • Pass Transistor (14I & SERF) • Asymmetric inputs (“non-inverter-like”) • Large stacks not compensated for (inverter)

  10. EE241 Spring 2009 Power-Performance Comparison:Mirror vs Bridge 32-bit Mirror Adder Same power but Mirror Adder faster! 32-bit Bridge Adder

  11. EE241 Spring 2009 Conclusion • Results • Mirror adder most practical (best performance) • Pass transistor logic more susceptible • Pros vs. Cons • Overall power dissipation still much lower than standard CMOS technology • Possible area issues (independent trenches)

  12. EE241 Spring 2009 Future Work • Other Full Adders: • Dynamic • Other Adder Topologies: • Carry Look-ahead Adder • Carry Bypass (Skip) Adder • Carry Select Adder • Energy-Delay Optimization • Questions?

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