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## Lecture 17: Adders

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**Outline**• Datapath • Computer Arithmetic Principles • Single-bit Addition • Carry-Ripple Adder • Carry-Skip Adder • Carry-Lookahead Adder • Carry-Select Adder • Carry-Increment Adder • Tree Adder 17: Adders**A Generic Digital Processor**17: Adders**Building Blocks for Digital Architectures**• Arithmetic unit • Bit sliced data path – adder, multiplier, shifter, comparator, etc. • Memory • RAM, ROM, buffers, shift registers • Control • Finite state machine (PLA, random logic) • Counters • Interconnect • Switches, arbiters, bus 17: Adders**An Intel Microprocessor**17: Adders**Bit-Sliced Design**17: Adders**Bit-Sliced Datapath**17: Adders**Itanium Integer Datapath**17: Adders**Motivation**• Arithmetic units are, among others, core of every data path and addressing unit. • Data path is at the core of • microprocessors (CPU) • signal processors (DSP) • data processing application specific IC’s (ASIC) and programmable IC’s (FPGA) • Standard arithmetic units available from libraries • Design of arithmetic units necessary for • non-standard operations • high performance components • library development 17: Adders**Naming Conventions**• Signal busses: A (1-D), Ai, (2-D), ai:k (sub-bus, 1-D) • Signals: a, ai (1-D), ai,k (2-D), Ai:k (group signal) • Circuit complexity measures: A (Area), T (cycle time, delay), AT (area-time product), L (latency, number of cycles). • Arithmetic operators: +, -, •, /, log (=log2) • Logic operators: OR, AND, XOR, NOT, … 17: Adders**Circuit Complexity Measures**• Unit gate model • Inverter, buffer: A = 0, T = 0 • Simple monotonic 2-input gates (AND, OR, NAND, NOR): A = 1, T = 1 • Simple non-monotonic 2-input gates (XOR, XNOR): A = 2, T = 2 • Simple m-input gates: A = m – 1, T = • Wiring not considered • Only for estimation purposes 17: Adders**Recursive Function Evaluation**• Given: inputs ai, outputs zi, function f (graph sym. •) • Non-recursive functions (n.) • Output zi is a function of input ai • Parallel structure 17: Adders**Recursive Function Evaluation**• Recursive functions (r.) • Output zi is a function of all inputs ak, k ≤ i • with a single output z = zn-1 (r.s.): • f is non-associative (r.s.n) • serial structure • f is associative (r.s.a) • serial or single-tree structure 17: Adders**Recursive Function Evaluation**• Output zi is a function of all inputs ak, k ≤ i • multiple outputs zi (r.m.) (=> prefix problem) • f is non-associative (r.m.n) • serial structure • f is associative (r.m.a) • Serial or multi-tree structure • Shared tree structure 17: Adders**Arithmetic Operations**• Overview 17: Adders**Overview of Arithmetic Operations**• Direct implementation of dedicated units • always: 1 – 5 • in most cases: 6 • sometimes: 7, 8 • Sequential implementation using simpler units and several clock cycles (decomposition) • sometimes: 6 • in most cases: 7, 8, 9 • Table look-up techniques using ROMs • universal: simple application to all operations • efficient only for single-operand operations of high complexity (8 - 12) and small word length. 17: Adders**Overview of Arithmetic Operations**• Approximation using simpler units: 7 – 12 • Taylor series expansion • polynomial and rational approximations • convergence of recursive equation systems • CORDIC (COordinate Rotation DIgital Computer) 17: Adders**Binary Number Systems**• Radix-2, binary number system (BNS): irredundant, weighted, positional, monotonic. • n-bit number is an ordered sequence of bits (binary digits) • Simple and efficient implementation in digital circuits • MSB/LSB (most/least significant bit): an-1/a0 • Represents an integer or fixed point number, exact. • Fixed point numbers: m-bit integer n-m bit fraction 17: Adders**Binary Number Systems**• Unsigned: positive or natural numbers • Value: • Range: • Two’s (2’s) complement: standard representation of signed or integer numbers • Value • Range 17: Adders**Binary Number Systems**• Complement: • Sign: an-1 • Properties: asymmetric range, compatible with unsigned numbers in many arithmetic operations. (same treatment of positive and negative numbers) • One’s (1’s) complement: similar to 2’s complement • Value: • Range: 17: Adders**Binary Number Systems**• Complement: • Sign: an-1 • Properties: double representation of zero, symmetric range, modulo (2n-1) number system. • Sign-magnitude: alternative representation of signed numbers • Value: • Range: • Complement: 17: Adders**Binary Number Systems**• Sign: an-1 • Properties: double representation of zero, symmetric range, different treatment of positive and negative numbers in arithmetic operations, no MSB toggles at sign changes around 0 (=> low power) 17: Adders**Gray Numbers**• Gray numbers (code): binary, irredundant, non-weighted, non-monotonic. • Property: unit-distance coding. Exactly one-bit toggles between adjacent numbers. • Applications: counters with low output toggle rate (low power busses), representation of continuous signals for low-error sampling (no false numbers due to switching of different bits at different times). • Non-monotonic numbers: difficult arithmetic operations (addition, comparison). 17: Adders**Gray Numbers**• Binary - Gray conversion • Gray – binary conversion 17: Adders**Redundant Number Systems**• Non-binary, redundant, weighted number systems. • Digit set larger than radix (typically radix 2) => multiple representations of the same number => redundancy. • No carry propagation in adders => more efficient implementation of adder-based units (multipliers, dividers, etc.) • Redundancy => no direct implementation of relational operators => conversion to irredundant numbers. • Several bits used to represent one digit => higher storage requirements. • Expensive conversion to irredundant numbers. Not necessary if redundant input operators are allowed. 17: Adders**Delayed-Carry Representation**• Delayed-carry or half adder representation • 1 digit holds the sum of 2 bits (no carry out) • Example: 01 + 01 = (0,0) (1,0) = 2 17: Adders**Carry-Save Representation**• One digit holds the sum of 3 bits or 1 digit and 1 bit. No carry-out digit, carry is saved. • Standard redundant number system for fast addition. 17: Adders**Signed-Digit Representation**• Signed-digit (SD) or redundant digit (RD) number representation. • No carry propagation in S = R + T • One digit holds the sum of two digits. No carry-out. 17: Adders**Signed-Digit Representation**• Minimal SD representation: minimal number of non-zero digits. • Applications: sequential multiplication (less cycles), filters with constant coefficients (less hardware). • Example: minimal 17: Adders**Signed-Digit Representation**• Canonical SD representation: minimal SD. Not two non-zero digits in sequence. • SD -> binary: carry propagation necessary => adder. • Other applications: high speed multipliers. • Similar to carry-save, simple use for signed numbers. 17: Adders**Residue Number Systems**• Non-binary, irredundant, non-weighted number system. • Carry-free and fast additions and multiplications. • Complex and slow other arithmetic operations (e.g. comparison, sign, and overflow detection) because digits are not weighted. Conversion to weighted mixed-radix or binary system required. • Codes for error correction and detection. • Possible applications (but hardly used) • Digital filters • Error detection and correction 17: Adders**Residue Number Systems**• Base is n-tuple of integers (mn-1, mn-2, …, m0), residues (or moduli). These mi are pairwise prime. • Arithmetic operations: each digit computed separately. 17: Adders**Residue Number Systems**• Best moduli mi are 2k and 2k – 1. • High storage efficiency with k bits. • Simple modular addition k bit adder without cout 17: Adders**Residue Number Systems**• Example: 17: Adders**Floating-Point Numbers**• Larger range, smaller precision than fixed-point representation, inexact, real numbers. • Double-number form => discontinuous precision. • S | biased exponent E | unsigned norm mantissa M • Basic arithmetic operations 17: Adders**Floating-Point Numbers**• Basic arithmetic operations based in fixed point add, multiply, and shift operations. Post-normalization required. • Applications: • Processors: real floating point formats (e.g. IEEE standard), large range due to universal use. • ASICs: usually simplified floating-point formats with small exponents, smaller range. Used for range extension of normal fixed-point numbers. • IEEE floating point format: 17: Adders**Logarithmic Number System**• Alternative representation to floating point (mantissa + integer exponent -> only fixed point exponent). • Single number form => continuous precision => higher accuracy, more reliable. • Basic arithmetic operations: • (A < B) = (EA < EB) additionally consider sign • A + B by approximation or addition in conventional number system and double conversion. 17: Adders**Logarithmic Number System**• Basic arithmetic operations • Simpler multiplication, exponentiation. More complex addition. • Expensive conversion: (anti)logarithms probably by table look-up. • Applications: real-time digital filters. 17: Adders**Antitetrational Number System**• Tetration (t.x = and antitetration (a.t.x) • Larger range, but smaller precision than logarithmic representation. Otherwise, analogous. • Note that all these systems can be mixed in composite arithmetic. • Choice of number representation should be hidden from the user. The compiler should handle it. • Rational numbers can also be represented in floating slash notation. 17: Adders**Round-Off Schemes**• Intermediate results with d additional lower bits. This results in higher accuracy. • Rounding: keeping error e small during final word length reduction: • Trade-off: numerical accuracy vs implementation cost. • Truncation • = average error e • Round to nearest (normal rounding) 17: Adders**Round-Off Schemes**• Round to nearest • The error is nearly symmetric • + 0.12can often be included in a previous operation. • Round to nearest even/odd • bias = 0 (symmetric) • Mandatory in IEEE floating-point standard • 3 guard bits for rounding after floating point operations: guard bit G (postnormalization), round bit R (round to nearest ), sticky bit S (round to nearest even) 17: Adders**Addition**17: Adders**Single-Bit Addition**Half Adder Full Adder 17: Adders**1-Bit Adders**• Add up m bits of same magnitude • Output the sum as a k-bit number ( ) • Or count 1’s at inputs => (m,k) counter – combinational counter. • A half adder is a (2,2) counter 17: Adders**1-Bit Adders**17: Adders**1-Bit Adders**• A full-adder is a (3,2) counter. 17: Adders**PGK**• For a full adder, define what happens to carries (in terms of A and B) • Generate: Cout = 1 independent of C • G = A • B • Propagate: Cout = C • P = A B • Kill: Cout = 0 independent of C • K = ~A • ~B 17: Adders**Full Adder Design I**• Brute force implementation from eqns 17: Adders**Full Adder Design II**• Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) • Critical path is usually C to Cout in ripple adder 17: Adders**Full Adder Design II**• Same circuit with sized transistors 17: Adders