Senior Design Project Tempest Code Project

1. Senior Design Project Tempest Code Project Group # 12 Anthony Wagner Jerome Tunaya Toeun Ly

3. Project Overview Simulate Atari�s Tempest via VHDL 1) Convert Atari Arcade hardware to Software using original schematics and the VHDL language 2) Load synthesizable VHDL component (6502 processor) onto FPGA.

4. Requirements Accurate VHDL Smartmodel Simulation of the major components of the Atari Vector Graphics Arcade Hardware: 6502 Microprocessor Vector State Generator Mathbox (AMD 2901 Bit Slice Processor) Load FPGA with 6502 microprocessor code to show understanding of the FPGA process.

5. Benefits Problem: Hardware for original arcade game is outdated, finding replacement parts and repairing original hardware can be hard and/or expensive. Solution: By converting the hardware to VHDL, in time, entire components of the Tempest Arcade game could be placed on a single FPGA chip, allowing for an alternative, cheaper source of replacement for hardware. Problem: Original Arcade hardware was stored in a large, heavy cabinet, with dedicated monitor and speakers. Solution: Will allow for future use on alternate platforms (Personal Computer)

7. Other Emulators There are other emulator projects similar to this project already released: The Tempest Code Project The Tempest Emulator in Java - Norbert Kehrer (April 2001) MAME (Multiple Arcade Machine Emulator)

8. How did this help us? These other projects have source code and other resources available on the web. The Tempest Code project has Tempest in Assembly Language, helpful in testing of the 6502 microprocessor.

9. Field Programmable Gate Array (FPGA) Chip

10. Field Programmable Gate Array (FPGA) Chip Holds from 64 to 10,000 identical logic cells. Each one of these logic cells can take on a certain logic function from a specified set of functions. These cells are connected to each other by a matrix of wires and programmable switches. With the logic cells each taking on a different logic function, the array can emulate blocks of logic circuits.

11. Why use FPGA? FPGA is fully customizable, as opposed to a manufactured chip. Most chips are fabricated by the Manufacturer according to the specifications of the consumer. The consumer cannot alter the design of the chip. �Field Programmable� means programmable in the field, i.e. Gates can be programmed and reprogrammed by the consumer.

12. Cons to FPGA With the board we used, the Altera Flex10K, the chip loses the embedded programming once power is cut. The board we used is not able to be connected to the ROM and RAM chips, so we had to manually input signals and check for correct output for testing.

13. FPGA Smartmodel Simulation cannot be Synthesized for FPGA use. To show FPGA capability, we have loaded the 6502 processor onto the Altera board and tested it extensively.

14. Xilinx Spartan FPGA XCS05 238 Logic Cells 5,000 Max System Gates 100 total 10 x 10 CLB arrays 360 Flip-Flops 77 Maximum User I/O 3,200 Total RAM bits Very Low Cost Unlimited Reprogrammability Fully Supported by Xilinx development Software Too complex for what we were planning to use it for

15. Altera Flex10K Easy to use interface Free software Used in Engineering Technology Classes at UCF Acquired for use, free of charge Complex enough for 6502 microprocessor to be loaded into it

16. Hardware Components

17. Mathbox Performs 3-D Calculations needed to alter the perspective in the game. Uses AMD 2901 ALU Processor to perform calculations

18. Mathbox Schematic

20. AMD 2901 Has 9 bits for Instructions:

21. AMD 2901

22. AMD 2901 Reads information stored in Mathbox ROMs, which perform appropriate calculations for redrawing based on player input and Computer A.I. (for enemy movement. Reads appropriate info based on Address Bus, alters data on Data Bus.

23. Mathbox simulation If we were to do full emulation of the Arcade game, Mathbox emulation would be needed. Smartmodel VHDL simulation was acceptable.

24. Used with permission from 6502.orgCPU/6502 ProcessorToeun Ly

25. Why the 6502A and not 6502? 6502A runs much faster than its predecessor the 6502. 6502 is rated for 1.0 MHz 6502A is rated for 1.5 MHz. This increase in speed is needed for Tempest to run properly and smoothly. We can easily derive the clocks in VHDL by using a process. Example: 1/1.5MHZ = 666.666 ns We can use a process to make the clock. Here is the code for the clock: Signal Clk:=�1�; --initialize the clock process (Clk) begin if Clk =�1� then Clk <= �0� after 333.333 ns, �1� after 666.666 ns; end if; end process;

26. 6502A Microprocessor Runs at 1.5 MHz 56 total instructions set 16 address lines 8 Data lines 13 different addressing mode - A (accumulator) - X,Y - S (stack pointer) - PC (Program counter) - Status register Courtesy of http://roger.trideja.com/c64/

27. Instruction Registers 256 bytes are allotted in the first page for the microprocessor. Three usable registers 8-bit registers (A, X, Y) Makes programming difficult for tempest programmers. Since it is too time-consuming to actually code the entire 6502 Microprocessors ourselves we decided to use one that was already coded in VHDL.

28. Free-ip.com Opencores.org From Designer Written in VHDL 56 instructions Error-free and tested extensively. Used in a variety of projects before. Old Not Cycle-Accurate Written in VHDL 56 instructions Has bugs and not been tested Has not been used in any major projects yet. Newer Cycle-Accurate Can also emulate the 65C02 and the 65C816

29. Chose Opencores.org Main Reason: Very important for it to be cycle-accurate because Tempest depends on it to work properly and it�s free. Extensive Debugging had to be completed because some of the instructions did not run properly. There were also some errors with some of the cycles for the instructions. (i.e. BEQ did not branch when the zero flag was set) To fix the problems and errors, an extensive and exhaustive test was made in order to test each and every instructions and case. Once an error was found we had to go through the code and debug it and try to fix it. One error can mean that the microprocessor can be unpredictable and sacrifice the success of the entire project. So we had to test all 56 instructions out to make sure that it was doing what it suppose to do. Wrote several assembly programs (Included in the Packet).

30. CLOCK CIRCUIT A 12 MHz crystal oscillator was used to derive all the clocks. 1.5Mhz, 3Mhz, 6Mhz, 3Khz, 12 Khz, 24 Khz 3 MHZ is needed for the Watchdog, SINP and AUX board.

32. Power Reset and Watchdog Counter Makes sure that the CPU is not stalling and that it�s doing something. (Typical causes of errors could be an open or shorted address or data bus lines, bad ROMs or RAMs, bad chip, bad bus buffers, etc. ) It works by requiring the Tempest programmers to reset the Watchdog Counter at different times in the program. (i.e. after a BNE instruction that loops around for a long time.) If the WDCLR_N is not set for a long time the whole game reset. This prevents the game from locking up. The watchdog is fed from the 3 KHz source. Since it also includes D4 it will be divided by 256. This means that in order for the program to run properly it must access location 5000 at least once every 80 Msec to avoid being reset.

34. IRQ COUNTER

35. Address decoder Needed to decode the Address bits to see what data is being read or written to the Data bus. Microprocessor reads Data from several sources including the CPU ROMs and RAMs, Vector ROMs and RAMs, MATHBOX ROMs and RAMs and switches and controller, etc�

37. Memory Map Used to show what should be read from the Data line or written into the Data line when the Address is decoded.

38. Specifications 6502A Type: Microprocessor Manufacturing: process: N-channel, silicon gate, depletion load technology Package: 40-pin plastic DIP Speed: 2Mhz On-Chip peripherals: Clock Oscillator Physical memory: 64Kb Min/Max Temp: 0-70 Degrees Max Power Dissipation: 0.7 watts Costs $10

39. Pokey ChipResponsible for making the sounds and controlling the randomness of the game. There were some problems with making it random so we had to check inside of the MAME source code to see what they did in order to make the game random.Pokey #1 has $60CF and Pokey #2 has $60DF and they both have to hold the value �3� or 11Bin. This will zero out the frequency and controlfor each channel. We will later show in the simulation where Tempests cleared out the Pokey chips.

40. Coin Switch Responsible for setting switches and deciding if it�s one player or two players or in Test or Diagnostic modes. Decides when the game will begin and how many players are playing. We emulated it by saying that after a certain time amount of time the coin switch will be turned on. i.e. Right_Coin_Switch <= �1� after 1000000000 ns else =�0�; --After resetting, the game will wait for a coin to drop in order to start. For the sake of simulation we simulated a coin to be dropped at 1,000,000,000 ns or 1 second in real time. When this happens it should cause the vector generator to go and start drawing the shapes for the game.

41. Coin Switches

43. Testing the 6502 In order to be sure that the 6502 was executing the instructions in the ROMs correctly we had to trace through the instructions line by line. A group was founded online called �Code Tempest Project� and they had the Tempest ROMs already disassembled. We looked through this code and compared them to what our ROMs looked like and they matched almost perfectly. The next thing we did was go through all the assembly op codes and checked it with the Scirocco simulator to make sure it was running the instructions as planned and there there�s no errors in the microprocessors or the ROMs. It worked! All of the instructions ran smoothly.

44. VECTOR STATE MACHINE Anthony Wagner

45. Vector State Machine The vector state machine has its own instruction set comprised of nine instructions. Of those nine instructions all but one is two bytes long. The vector machine has its own section of RAM and ROM that are each 4K. The Vector RAM is located in bytes 2000 � 2FFF and the Vector ROM is located at bytes 3000 to 3FFF. The Vector State Machine controls what color the drawing is, the broadness or thickness of the drawing, whether the beam is on or off, and whether the drawings are in the x or y directions on the Vector State Monitor.

46. Instruction Set The Actual length of LDRAW is the length divided by two. The main game processor fills the vector RAM with a list of instructions telling the AVG where to draw vectors on the display, and then writes to the VGGO address port which starts the AVG executing. There are 8 basic colors from the RGB bits and 256 intensity levels of these 8 colors. something to do with the fact that a long vector drawn in the same time period as a short vector will need to have more intensity to give the same apparent intensity on the screen. The Actual length of LDRAW is the length divided by two. The main game processor fills the vector RAM with a list of instructions telling the AVG where to draw vectors on the display, and then writes to the VGGO address port which starts the AVG executing. There are 8 basic colors from the RGB bits and 256 intensity levels of these 8 colors. something to do with the fact that a long vector drawn in the same time period as a short vector will need to have more intensity to give the same apparent intensity on the screen.

47. STACK PROGRAM COUNTER

48. STACK PC COUNTER The Stack and program counter is used to jump to addresses during jump instructions and to save addresses values to the stack. Addresses can be popped off the stack later to return from a subroutine. The LS 193 counter controls whether the registers are written to or read from and which place in the register to do this. The counters to the right mostly are used as the program counter if they are not receiving and loading the DVY lines or the lines coming from the registers which may contain an address to go to.

49. Addressing for State Machine The Vector Generator addresses its instructions in a peculiar way. Not in order as most processors. The first address of any instruction is on the odd byte and then back to the even byte. Therefore it is always addressing odd to even. 4000 00 The machine executes the 4001 45 addresses in the following way. 4002 25 4003 40 4001,4000,4003, 4004 25 4002,4005,4004 We are going to program the pc exactly how it works as shown. Changing the order of the bytes will cause errors when a jump or subroutineWe are going to program the pc exactly how it works as shown. Changing the order of the bytes will cause errors when a jump or subroutine

50. VECTOR GENERATOR ADDRESS SELECTOR

51. VECTOR GENERATOR ADDRESS SELECTOR The signals coming into the Ls 157�s either come from the stack and program counter or they come from the 6502. Thirteen address bits are taken from the Microprocessor if the selector signal is zero, if the selector signal is one the stack and pc�s signals are taken. These often act as the program counter. The signals coming in have to do with the enabling of RAM�s or ROM�s.

52. Vector State Addressing contd.. The vector state machines ROM and RAM interact with the 6502 which uses a 16 bit address. How does the vector instruction jump that has 13bits for the effective address get to its next instruction or data? To compensate for the difference in the bits the address from the instruction is shifted left by one bit and a binary one is shifted into the least significant bit.

53. Addressing Example Two bytes F8 and 58 are fetched which constitute the Jump instruction F8 58 = 1111 1000 0101 1000 Op code = 111 Address =1 1000 0101 1000 The address is shifted left by 1 bit and a binary �1� is put into the least significant bit. 11 0000 1011 0001 Two zero�s are placed into the first byte yielding 0011 0000 1011 0001 = 30B1 Hex 30B1 is a location in the Vector State ROM

54. VECTOR ROM/RAM

55. VECTOR ROM and RAM The 8 RAMs each have 10 input lines and 4 output lines. The ROMs have 11 input lines and 8 output lines. The vector rom or ram is enabled by the VGAS box and the Vector Write_n signal allows a read or write from RAM. The 6502 writes to the vector generator RAM and can also receive data from the vector generator.

56. STATE MACHINE The State Machine controls the Latch and Strobe signals that are sent to almost every other box in this vector system. The State Machine has a ROM chip that at addresses below 10000000 gives an output of 0000. All addresses greater than that have different data values. Both GO and HALT signals need to be zero so that the State Machine is active. Once the ROM is active it will remain in a continuous loop changing latch and strobe signals, if the op codes change the ROM will start a different loop. All loops will end if Halt or GO is one. This loop continues changing values on the decoder if VMEM is one. After a simulation I found out that the flip flop signal from the state machine control acts as a clock signal and forces a the loop to go on if the A7 bit of the SMROM is 1.

57. Testing the Vector Generator The Understanding of signals coming from the 6502 schematic sheet was important. Reset the circuit ,Write to RAM start a VGGO watch to see if AVG addresses are recognizable. Check output to see if a draw was executed.

58. Administration Toeun Ly

59. Workload

60. Milestones

61. COSTS FPGA chip/Altera board � sponsored by Dr. Coowar FPGA software � Sponsored by Dr. Coowar 6502A Microprocessor � $10 VHDL software(synopsys) � Sponsored through education license

62. SIMULATION We will now show you the simulation of the game that we videotaped. The reason why we couldn�t simulate it here is because of two reasons: The Synopsys�s Scirocco program only runs on Linux computers. The simulations takes a very long time to run. (We ran it for 1,000,000,000 ns or 1 sec and it took us over 6 hours) We will also show the simulation for the FPGA chip that we�ve programmed to use the 6502 microprocessor. This is to show that we know how to synthesize and program a microprocessor in the FPGA chip. Due to miscommunication with our Sponsor we did not realize that the smartmodel chips that we were using were not synthesizable to be used on an FPGA chip. In lieu of this we just synthesized the 6502 to show that we do have a working part in the FPGA and we do have the ability to program an FPGA. Other parts of the hardware can also be implemented in the FPGA but we have to reprogram almost the entire schematic again from scratch because we mostly used smartmodel for the simulations. We can not show the FPGA working here right now because it requires a Altera program that only can be used in the Engineering technology lab.

63. Things we�ve learned Improve our VHDL programming tremendously Experienced a hand-on approach on writing assembly code and dealing with errors and debugging. Make RTL level logic by using smartmodels and simulating them through Synopsys�s Scirocco. Learn how to program and synthesize FPGA chips. How to work together in groups to accomplished a task. Learn that not everything will go according to plan and that adjustments must be made in order to complete our tasks.

64. Questions? Anyone have any questions?