Pass Transistor Logic Cell Library

1. Pass Transistor LogicCell Library Group Members: Keith Benson Kofi Inkabi Ashley Nozine

2. Project Summary • Design basic cells that can incorporated into Cadence cell library. • Incorporate cells into Cadence’s cell library. • Compare technology mapped layout versus CMOS only Layout • Power • Area • Delay

3. Standard Cell Dimensions

4. Cell Characteristics • 0.25um technology • Area • Height * Width • Height is constant at 54  = 6.75um • Delay • 50% Input  50% Output • Dynamic Power dissipation • PDyn = VDD * Iave • Iave = (IHL + ILH) / 2

5. Cell Y2 schematic

6. Layout without Buffer

7. Simulation of Layout/no buffer

8. Cell Y2 no buffer: results

9. Cell Y2 with buffer schematic

10. Layout with small buffer

11. Simulation of Layout/Small Buf.

12. Cell Y2 small buffer: results

13. Cell Y2 with buffer*x schematic

14. Layout with large buffer

15. Simulation of Layout/Large Buf.

16. Cell Y2 large buffer: results

17. Original Schedule • A: Project Proposal • B: Learn Cadence/Know Cadence Library Specs. • C: Build Cell layouts • D: Measure Cells for Power, Area, and Power • E: Receive Netlist and automatically generate layout of Technology Mapped cells • F: Compare Layout of PTL and CMOS cells against CMOS only cells

18. Revised Schedule • A: Locate tool to automatically generate layout from Netlist • B: Receive Netlist and automatically generate layout of Technology Mapped cells • C: Characterize Technology Mapped layout from netlist • D: Characterize CMOS layout from netlist • E: Compare Technology Mapped layout vs. CMOS only layout • F: Final Report