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Analog Peak Detector and Derandomizer. G. De Geronimo, A. Kandasamy, P. O’Connor Brookhaven National Laboratory IEEE Nuclear Sciences Symposium, San Diego November 7, 2001. Multichannel Readout Alternatives. Direct digitization. Track-and-Hold + Analog Multiplex. Analog Memory

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analog peak detector and derandomizer

Analog Peak Detector and Derandomizer

G. De Geronimo, A. Kandasamy, P. O’Connor

Brookhaven National Laboratory

IEEE Nuclear Sciences Symposium, San Diego

November 7, 2001

multichannel readout alternatives
Multichannel Readout Alternatives

Direct digitization

Track-and-Hold

+ Analog Multiplex

Analog Memory

+ Analog Multiplex

  • most flexible
  • requires many fast ADCs
  • expensive, high power
  • requires trigger
  • has deadtime
  • timing uncertainty
  • requires sparsification
  • requires trigger
  • can be deadtimeless (complex control)
  • requires sparsification
peak detector pd

self-sparsifying

  • timing output
  • Drawbacks
  • accuracy impaired by op-amp offsets, CMRR, slew rate
  • poor drive capability
  • deadtime until reset
Peak Detector (PD)
  • Advantages
  • self-triggering
improved cmos pd using two phase configuration

Read phase

  • same op-amp re-used as unity-gain buffer
  • same CM voltage
  • op-amp errors cancel
  • enables rail-to-rail sensing
  • provides good drive capability
Improved CMOS PD Using Two-Phase Configuration
  • Write phase
  • conventional peak detector
  • M1: unidirectional current source
  • voltage on CH includes op-amp errors (offset, CMRR)
two phase peak detector in 0 35 m m cmos

LAYOUT

340 mm

50 mm

245 mm

50 mm

Two-Phase Peak Detector in 0.35 mm CMOS

SCHEMATIC

PD loop with switches

Switch control logic (data driven)

two phase cmos peak detector results
Two-Phase CMOS Peak Detector - Results

Waveforms

Absolute accuracy

Droop rate

Time walk

two phase cmos peak detector summary
Two-Phase CMOS Peak Detector - Summary
  • Self-triggering
  • 2-phase operation eliminates op-amp errors
    • High absolute accuracy independent of process, supply, temperature variation
    • Rail-to-rail input and output
  • Strong drive capability
  • No switch charge injection into hold node
  • Timing output

Parameter

Value

m

Technology

0.35

m CMOS DP4M

Supply voltage

3.3 V

Input voltage range

0.3

3 V

³

Absolute accuracy

0.2 %, t

500ns

p

0.7%, t

=200ns

p

± 2.3 ns, Vin < 2.5 V

Time walk

± 5 ns, Vin < 3 V

Droop rate

0.25 V/s

Power dissipation

3.5 mW

2

Cell area

0.03 mm

peak detector and derandomizer

B: PD plus SCA as analog buffer

C: PD with multiple hold capacitors

Topology A with two parallel PDs has been fabricated and tested.

A:Array of PD with ping-pong control

Peak Detector and Derandomizer
  • Combine the peak detect and analog hold functions of the PD with additional analog storage and control logic to create a Peak Detector– Derandomizer (PDD).
  • PDD behaves like a data driven, analog FIFO memory.
  • Topologies:
multichannel readout system with pdd
Multichannel Readout System with PDD

SSM: self-switched multiplexer; custom chip that detects above-threshold inputs and routes them to PDD input.

In response to a READ request from the DAQ system (pulser), the next peak sample stored in the PDD is presented to the 12-bit ADC.

After a fixed delay the pulser RESETs the PDD that was read out, freeing it to process next input pulse.

multichannel pdd readout system first results
Multichannel PDD Readout System: First Results
  • Input pulses from source occur randomly
  • READ process is synchronous 200 kHz
  • READ rate matches average input rate
  • Simultaneous readout and acquisition of new data
  • 2-sample buffer absorbs rate fluctuations
multichannel pdd readout system
Multichannel PDD Readout System

Spectra

Solid line: commercial MCA.

Points: PDD, single channel.

Circles: PDD, 16 channels gain-adjusted.

Resolution limited by CZT detectors.

Source Profile

241Am source centered over channel 2.

summary
Summary
  • New 2-phase peak detector in submicron CMOS:
      • High absolute accuracy (0.2%) and linearity (0.05%)
      • Rail-to-rail input and output
      • ± 2.3 ns time walk
      • Low power (3.5 mW)
      • Extremely compact (0.03 mm2)
  • A building block for compact, efficient multichannel readout system:
      • Self-triggered
      • Self-sparsifying
      • Deadtimeless
  • Peak detector – derandomizer (PDD) with 2-event buffer demonstrated:
      • First step towards data-driven analog FIFO readout