Florian Braun, Henry Fu Washington University Applied Research Lab Supported by: NSF ANI-0096052

1. The Layered Protocol Wrappers:A Solution to Streamline Networking Functions to Process ATM Cells, AAL5 Frames, IP Packets, and UDP Datagrams Florian Braun, Henry Fu Washington University Applied Research Lab Supported by: NSF ANI-0096052 and Xilinx Corp. http://www.arl.wustl.edu/arl/projects/fpx/wrappers/ florian@arl.wustl.edu, hwf1@arl.wustl.edu

2. The Layered Protocol Wrappers • The Layered Protocol Wrappers Library • A circuit that streamline the networking functions to process ATM cells, AAL5 frames, IP packets, and UDP datagrams • A layered design that consists different processing circuit in each layer • Allows application to be implemented at a level where important details are exposed and irrelevant details are hidden

3. Basic Concept of the Protocol Wrappers Application Wrapper Wrapper

4. Overview of the Protocol Wrappers • The Protocol Wrappers is composed of four circuits: • Cell Processor processes raw ATM cells between network interfaces • Frame Processor processes variable length AAL5 frames • IP Processor processes IP packets • UDP Processor sends and receives UDP datagrams

5. Overview of the Layered Protocol Wrappers UDP Processor IP Processor Frame Processor Cell Processor Interfaces to Off-Chip Memories Application-level Hardware Module Data Input Data Output

6. The Cell Processor • The Cell Processor handles ATM Cells, and provides valid ATM Cells control signals to the cell level application or the Frame Processor • Checks the HEC and drops erroneous cells • Dispatch cells to application or bypass • Handles control cells • Recomputes HEC for outgoing cells

7. The Cell Processor (More) • Data Flow inside the Cell Processor App or Frame Processor HEC Dispatch Check HEC Set Control Cells

8. The Frame Processor • The Frame Processor handles AAL5 frames and provides valid AAL5 frame control signals to the application or the IP Processor • Detects AAL5 frame boundaries • Handles CRC • Segments data into cells

9. The Frame Processor (More) • Data Flow inside the Frame Processor Cell App or IP Processor Frame Segment AAL5CRC AAL5CRC Detection ation

10. The IP Processor • The IP Processor handles IP packets and provides valid IP packet control signals to the application or the UDP Processor • Verify IP version • Check Header Checksum for application • Drop packet if the Header Checksum fails • Decrease TTL field (ev. ICMP msg) • Signal start of payload (SOP) • Recompute Header Checksum

11. The IP Processor (More) • Data Flow inside the IP Processor IP Detect App or UDP Processor TTLDec Checksum + Checksum

12. The IP Processor (More) • The IP Packet is encapsulated by a ATM Cell ATM Header Ver HL ToS Packet Length IPID Fragment TTL Proto Checksum IP Header Source IP address Destination IP address Payload

13. The UDP Processor • The UDP Processor handles UDP datagrams and provide valid UDP datagram signal to the application • Check for protocol ID (17) • Signal start of datagram (SOD) • Handle UDP checksum

14. The UDP Processor (More) • Data Flow inside the UDP Processor Set App or UDP Processor UDP Checksum Detect

15. The UDP Processor (More) • The UDP Datagram is encapsulated by a IP Packet inside an ATM Cell ATM Header Ver HL ToS Packet Len IPID Fragment IP Header TTL Proto Checksum Source IP address Destination IP address Src Port Dest Port UDP Header Length Checksum Payload

16. Synthesis Results Space/LUTs Speed/MHz Cell Processor 781 125 Frame Processor 1251 116 IP Processor 1009 109 UDP Processor 550 114 • Required Space and Speed of the Layereed Protocol Wrappers

17. Performance Results Delay for short packages Delay for long packages Input Output Input Output Cell Processor 4 6 4 6 Frame Processor 21 22 10 31 IP Processor 36 39 24 197 UDP Processor 39 44 27 202

18. The Layered Protocol Wrappers Package • The Protocol Wrappers Package • Detailed Information • http://www.arl.wustl.edu/arl/projects/fpx/wrappers • Downloadable TAR File • http://www.arl.wustl.edu/arl/projects/fpx/wrappers/-wrappers.tar • Technical Report • http://www.arl.wustl.edu/arl/projects/fpx/wrappers/-wucs-01-10.pdf

19. Contents of the Layered Protocol Wrappers • Access the Protocol Wrappers Package • Cell Processor • cellwrapper.vhdl, the VHDL instantiation file • cellproc_sim.vhd, the VHDL simulation file • cellproc.edn, the EDIF Macro synthesis file • Frame Processor • framewrapper.vhdl, the VHDL instantiation file • frameproc_sim.vhd, the VHDL simulation file • frameproc.edn, the EDIF Macro synthesis file

20. Contents of the Protocol Wrappers Package • IP Processor • ipwrapper.vhdl, the VHDL instantiation file • ipproc_sim.vhd, the VHDL simulation file • ipproc.edn, the EDIF Macro synthesis file • UDP Processor • udpwrapper.vhdl, the VHDL instantiation file • udpproc_sim.vhd, the VHDL simulation file • udpproc.edn, the EDIF Macro synthesis file • COREGEN Components

21. Combining Multiple Processors • Cell Processor only • Cell Processor • Cell + Frame Processors • Frame Wrapper • Cell + Frame + IP Processors • IP Wrapper • Cell + Frame + IP + UDP Processors • UDP Wrapper

22. Wrappers Example: An UDP Application UDP Application Output Input UDP Processor IP Processor Frame Processor Cell Processor UDP Wrapper

23. Building an UDP Application • The user only needs to handle input signals from the UDP Wrapper • Input Signals: • D_MOD_IN (data input) • DataEn_MOD_IN (data enable) • SOF_MOD_IN (start of frame) • SOD_MOD_IN (start of datagram) • EOF_MOD_IN (end of frame) • TCA_MOD_IN (congestion control)

24. Building an UDP Application (More) • Similarly, the user only needs to handle output signals to the UDP Wrapper • Output Signals: • D_OUT_MOD (data output) • DataEn_OUT_MOD (data enable) • SOF_OUT_MOD (start of frame) • SOD_OUT_MOD (start of datagram) • EOF_OUT_MOD (end of frame) • TCA_OUT_MOD (congestion control)

25. Building an UDP Application (More) • Other important input signals • CLK • Clock signal for module • 100 MHz • Reset_l • Synchronous reset • Low for 1 clock cycle to reset state machines • Set by reconfiguration logic

26. Explanation of Control Signals • SOF_MOD_IN + SOF_OUT_MOD • High for 1 clock cycle during first ATM header word • Signals start of a new AAL5 frame • Note: HEC is not sent after this signal • EOF_MOD_IN + EOF_OUT_MOD • High during 1 clock cycle of last payload word of datagram • Followed by the two trailer words of the AAL5 frame

27. Explanation of Control Signals (More) • DataEn_MOD_IN + DataEn_OUT_MOD • High during valid payload data • High during trailer words (after EOF) • SOD_MOD_IN + SOD_OUT_MOD • High for 1 clock cycle during first word of UDP header • UDP payload starts after two valid payload words (check Data Enable) • Not enabled if not a UDP packet

28. Explanation of Control Signals (More) • D_MOD_IN + D_OUT_MOD • 32 bit wide data bus • TCA_MOD_IN + TCA_OUT_MOD • TCA signal is high when data can be accepted, low if no data should be sent • Wrappers back-propagate TCA to the NID • Data in pipeline will still be forwarded (~cell time) • IP wrapper has big packet buffer for outgoing data

29. Diagram of Input Signals CLK A A I I I I I U U D D D D D - - A A D D D D D D D P P P F F - - Data Cell Level SOC A - I I I I I U U D D D D D - - - - D D D D D D D F F - - - - - Data DataEn IP Level Frame Level SOF EOF SOP/ SOD A ATM Header I IP Header D Payload Data - Don't care U UDP Header P Padding F Frame Trailer

30. Wrapper Example: A Pass-through Circuit • The Protocol Wrappers Example Package • Visit • http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/ • Download the package • Right click on WrapperExample.tar.gz • Save it to h:\ • Start Cygwin Bash Shell • Engineering > FPGA Tools > Cygwin Bash Shell

31. Wrappers Example: A Pass-through Circuit • Extract the tar file • cd /cygdrive/h/ • gunzip WrapperExample.tar.gz • tar xvf WrapperExample.tar • cd WrapperExample • Examine the content of the package • WrapperExample/sim/, simulation directory • WrapperExample/syn/, synthesis directory • WrapperExample/vhdl/, vhdl source directory • WRapperExample/wrappers/, Wrappers directory

32. Input / Output Signals of the Module Clock & Reset Enable & Ready Cell Input Interface Cell Output Interface ENTITY ExampleModule IS PORT ( -- Clock & Reset clk : in STD_LOGIC; -- 100MHz global clock reset_l : in STD_LOGIC; -- Synchronous reset, asserted-low -- Enable & Ready -- Handshake for module reconfiguration. enable_l : in STD_LOGIC; -- Asserted low ready_l : out STD_LOGIC; -- Asserted low -- Cell Input Interface soc_mod_in : in STD_LOGIC; -- Start of cell d_mod_in : in STD_LOGIC_VECTOR(31 downto 0); -- 32-bit data tca_mod_in : out STD_LOGIC; -- Transmit cell available -- Cell Output Interface soc_out_mod : out STD_LOGIC; -- Start of cell d_out_mod : out STD_LOGIC_VECTOR(31 downto 0); -- 32-bit data tca_out_mod : in STD_LOGIC; -- Test Data Output test_data : out STD_LOGIC_VECTOR(31 downto 0)); end ExampleModule;

33. Input / Output Signals of the UDP Wrapper Coming From Cell Interface Coming from Application Input Interface Going to Cell Interface Going To Application Interface component udpwrapper port ( CLK : in std_logic; -- clock Reset_l : in std_logic; -- reset Enable_l : in std_logic; -- enable Ready_l : out std_logic; -- ready SOC_MOD_IN : in std_logic; -- start of cell D_MOD_IN : in std_logic_vector (31 downto 0); -- data TCA_MOD_IN : out std_logic; -- transmit cell available D_OUT_APPL : out std_logic_vector (31 downto 0); -- data to appl DataEn_OUT_APPL : out std_logic; -- data enable SOF_OUT_APPL : out std_logic; -- start of frame EOF_OUT_APPL : out std_logic; -- end of frame SOD_OUT_APPL : out std_logic; -- start of datagram TCA_OUT_APPL : in std_logic; -- congestion control D_APPL_IN : in std_logic_vector (31 downto 0); -- data from appl DataEn_APPL_IN : in std_logic; -- data enable SOF_APPL_IN : in std_logic; -- start of frame EOF_APPL_IN : in std_logic; -- end of frame SOD_APPL_IN : in std_logic; -- start of datagram TCA_APPL_IN : out std_logic; -- congestion control SOC_OUT_MOD : out std_logic; -- start of cell D_OUT_MOD : out std_logic_vector (31 downto 0); -- data TCA_OUT_MOD : in std_logic); -- transmit cell available end component;

34. Input / Output Signals of the ExampleApp component ExampleApp port ( CLK : in std_logic; -- clock Reset_l : in std_logic; -- reset D_MOD_IN : in std_logic_vector (31 downto 0); -- data DataEn_MOD_IN : in std_logic; -- data enable SOF_MOD_IN : in std_logic; -- start of frame EOF_MOD_IN : in std_logic; -- end of frame SOD_MOD_IN : in std_logic; -- start of datagram TCA_MOD_IN : out std_logic; -- congestion control D_OUT_MOD : out std_logic_vector (31 downto 0); -- data DataEn_OUT_MOD : out std_logic; -- data enable SOF_OUT_MOD : out std_logic; -- start of frame EOF_OUT_MOD : out std_logic; -- end of frame SOD_OUT_MOD : out std_logic; -- start of datagram TCA_OUT_MOD : in std_logic); -- congestion control end component; Application only needs to handle UDP signals

35. Implementation of the ExampleApp • Examine the “exampleapp.vhd” • A flip-flop that passes data and control signals through • Can be extended to implement other more complex network control functions • Will be used as the framework for the coming ROT13 exercise

36. Simulating the ExampleApp • Modelsim is used to simulate the ExampleApp • Go to the simulation directory • cd WrapperExample/sim/ • Compile the module and start Modelsim • Make compile • Make sim • In Modelsim main window, type: • do testbench.do • run 3000

37. Simulating the ExampleApp (More) • The input data at the line card level

38. Simulating the ExampleApp (More) • The input data at the UDP Wrapper level

39. Simulating the ExampleApp (More) • The input data at the application level

40. Simulating the ExampleApp (More) • The output data at the application level

41. Simulating the ExampleApp (More) • The output data at the UDP Wrapper level

42. Simulating the ExampleApp (More) • The output data at the line card level

43. Conclusion • In this Layered Protocol Wrappers Example • Shows the components of the UDP Wrapper • Shows the function of the UDP Wrapper • Shows how to instantiate and use the UDP Wrapper • Examines the control signals at various levels of data processing • Sets up the framework for ROT13 exercise