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Single Crystal Silicon Wafer Manufacturing: School of Microelectronic Engineering

Learn about the significance of single crystal materials in IC manufacturing, the advantages of silicon, crystal structures, defects, wafer transformation from sand to high-purity silicon, and the processes involved in producing epitaxial wafers. Dive into crystal orientation, defects, and methods like Czochralski and Floating Zone for crystal pulling. Discover the intricate steps of ingot polishing, wafer sawing, and wafer finishing. Enhance your knowledge of epitaxial wafer production, a crucial yet costly phase in the manufacturing process. Uncover the complexities and precision behind every stage of silicon wafer manufacturing in this informative course by the School of Microelectronic Engineering.

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Single Crystal Silicon Wafer Manufacturing: School of Microelectronic Engineering

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  1. io Single Crystal Silicon Wafer Manufacturing School of Microelectronic Engineering

  2. Objectives School of Microelectronic Engineering

  3. Why Single Crystal Material? • Single crystal Si wafers the most commonly used semiconductor material in IC manufacturing. • In the original form, most solid materials exist in the form of amorphous or polycrystalline structures. • To make an industrial standard transistor, a single crystal semi- conductor substrate is required. This is due to the scattering of electron from the grain boundary can seriously affect the p-n junction characteristics. School of Microelectronic Engineering

  4. Why Silicon? ` • Abundant, 26% earth crust’s is silicon. One of the most abundant element on earth. • Can form a very stable and strong oxide and easy to grow. • Larger bang gap (compared to Ge), can tolerate a higher operation temperature, wider impurity range and higher breakdown voltage. School of Microelectronic Engineering

  5. ` School of Microelectronic Engineering

  6. Crystal Structure ` • Atomic structure of a single crystal Si unit cell • Crystal orientations are defined in Miller Indexes. MOS IC Bipolar IC School of Microelectronic Engineering

  7. Crystal Defects ` • Vacancy – missing atom from crystal lattice • Interstitial defect – extra atom in between normal lattice • Frenkel defect – vacancy and interstitial in pair • Dislocation – geometric fault School of Microelectronic Engineering

  8. School of Microelectronic Engineering

  9. Dislocation School of Microelectronic Engineering

  10. From Sand to Wafer ` School of Microelectronic Engineering

  11. From Sand to Wafer ` • 1st step: Crude Silicon or MGS (~ 99% poly-crystal silicon) School of Microelectronic Engineering

  12. From Sand to Wafer • 2nd step: High Purity TCS Formation (Trichlorosilane, SiHCl3) • MGS grinded into powder • MGS powder react with HCL to form TCS • TCS is purified up to 99.9999999% ` School of Microelectronic Engineering

  13. From Sand to Wafer ` • 3rd step: EGS (Electronic Grade Silicon) Formation – polycrystal form School of Microelectronic Engineering

  14. From Sand to Wafer • 4th Step: Crystal Pulling • EGS to be heated at high temperature and pulled using single- Crystal silicon seed. • 2 methods; • Czochralski (CZ) Method – larger diameter, lower cost, in situ doping. • Floating Zone (FZ) Method School of Microelectronic Engineering

  15. From Sand to Wafer • CZ Method School of Microelectronic Engineering

  16. From Sand to Wafer • CZ Method School of Microelectronic Engineering

  17. From Sand to Wafer • FZ Method School of Microelectronic Engineering

  18. FZ and CZ Comparison ` School of Microelectronic Engineering

  19. From Sand to Wafer • 5th Step: Ingot Polishing and Wafer Sawing • Ingot polishing to remove the grooves created during pulling • Wafer slicing School of Microelectronic Engineering

  20. From Sand to Wafer Typical Wafer Parameters School of Microelectronic Engineering

  21. 6th Step: Wafer Finishing • Grinding • Edge Polished • Slicing • Lapping • Polished • Process Control School of Microelectronic Engineering

  22. Epitaxial Wafer School of Microelectronic Engineering

  23. Epitaxial Wafer The most expensive process step, ~ USD 20 -100 per step compared to USD 1 per step for other process. School of Microelectronic Engineering

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