VTX Electronics Integration. E.J. Mannel Columbia University June 9, 2008. Outline. Ground Plan Power Systems Slow Control DCM-2 Status Rack Allocation Design and Safety Reviews Schedule Issues and Concerns. Ground Plan.
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June 9, 2008
Pixel ½ Ladder
Barrel 1 Stave
Pixel ½ Ladder
Barrel 2 Stave
PHENIX Clean Ground
Bias Power Systems
Mini-Pod evaluation system from Wiener/ISEG
0-500 V floating supplies
Precision voltage/current monitoring
Two crates required for VTX:
Crate 1: Pixels, 4 modules- 64 Channels
Crate 2: Strips, 3 modules- 48 Channels
Performance evaluation on pixel ½ ladder March-May '08
Integration evaluation June-July '08
PHENIX DAQ/ONCS Groups, ISU Summer Students
Regular meetings with PHENIX DAQ/ONCS group on slow control issues.
PHENIX DAQ/ONCS group will participate in bias supply integration evaluation, June-July '08
PHENIX DAQ/ONCS group working with C. Pancake on PIXEL FEM slow control integration, June-July '08
The DCM is the PHENIX standard interface between the detector front end electronics and PHENIX DAQ.
Optical interface development complete
FE3 Daughter board operational with current DCM
Currently being used for HBD
Available for system chain tests
BNL R&D funding for DCM-2 design and prototype fabrication in place- Q3 FY08.
Design work starting with fabrication completion expected by Q4 FY09
2 Racks assigned to VTX
Sufficient space for VTX
power crates and patch
Location ~10 meters
Procedures in place for internal reviews of electronics system designs starting at Pre-production stage.
Requires submission of:
Relevant Data Sheets/Manuals
Upon answering all issues from review, design is released for production
Electronics Design Reviews as required
Pixel System Safety Review: 3Q '08
Bias Supply Procurement: 4Q '08
Pixel Power Supply Design: 3-4Q '08
Pixel Power Supply Procurement: 2Q '09
DCM-2s for Pixel system delivered: 3Q '09
Cable/Fiber Planning/Installation: 1-3Q '09
Rack Installation: 2-3Q '09
Verifying noise performance of pixel/strip ladders in combined test.
Power system design needs to proceed quickly.
Rack space and cable plan highly integrated with other PHENIX upgrades.
Design schedule for DCM-2 tight for reading out Pixel system in Run-10.
Ground plan developed and being fine tuned.
Design of power systems has started.
Evaluation of Bias Supply system in progress
Procedure for design and safety reviews.
Production SPIRO board review completed
Preproduction pixel bus completed
Plans for comprehensive pixel safety review in progress
Ground one end of the stave to one ½ ladder.
Barrel 1 to north ½ ladder.
Barrel 2 to south ½ ladder.
Provide for a shield between barrels 2 and 3.
Option for aluminized mylar between barrels 2 and 3.
Floating Power supplies
Shared returns between ½ Ladders for LV
Optical connections to Pixel FEM
Collect FEM data
Zero suppressed data
Data Error/ Event Alignment checking
Alignment checking via L1 data or/and adjacent data link
Possibility for data processing
First stage of event building
we need to handle possible link errors associate with increasing radiation. It may not be practical any more to stop run when one link drop out during the run.
ALTERA STRATIX I EP1S30
8 optical links per DCM
ALTERA STRATIX II EP2S60
Data link in
FEM DCM link
80 MHz 16 bits/word 1.6Gbits/sec
8b/10b encoding method
choose Ti’s TLK2501 as de-serializer
2 Mbits for event data buffer
1 Mbits for processing buffer
30K logical element
old DCM has 1K Logical element per optical link
Data link out
STRATIX II has
1 Mbits for event data buffer
1.5 Mbits for processing buffer
20K - 60 K logical element
faster than STRATIX I
ALTERA STRATIX I EP1S30