Interconnect Working Group

1. Interconnect Working Group ITRS 2003 2 December 2003 Lakeshore Hotel Hsin Chu, Taiwan Christopher Case

2. ITWG Regional Chairs Japan Shinichi Ogawa Akihiko Osaki Taiwan Douglas CH Yu US Robert Geffken Christopher Case Europe Hans Joachim-Barth Joachim Torres Korea Hyeon-Deok Lee Hyun Chul Sohn Also at 2 Dec TSIA Bau-Tong Dai Calvin Hsueh

3. Agenda • Interconnect scope • Highlight of changes • Difficult challenges • Review of key issues on materials • Reliability • Technology requirements issues • Table updates • Interconnect performance • Last words

4. Interconnect scope • Conductors and dielectrics • Metal 1 through global levels • Starts at pre-metal dielectric (PMD) • Associated planarization • Necessary etch and surface preparation • Embedded passives • Reliability and system and performance issues • Ends at the top wiring bond pads • Predominantly “needs” based, with some important exceptions (k and resistivity)

5. Typical MPU cross section

6. 2003 highlights • Significant changes • Changes to low k dielectric roadmap • Metal one MPU driver matched to overall nodes • Clarification of metal one versus local wiring • Maximum metal levels raised to 14 for MPU • Updated wiring performance metrics • Updated Jmax specification • Elimination of Imax specification • Inclusion of Pre metal dielectric requirements • Increased emphasis on reliability issues associated with Cu/low k integration • Expanded treatment of New Concepts

7. Introduction of new materials to meet conductivity requirements and reduce the dielectric permittivity* Engineering manufacturable interconnect structures compatible with new materials and processes* Achieving necessary reliability Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required to achieve necessary circuit performance and reliability. Manufacturability and defect management that meet overall cost/performance requirements Mitigate impact of size effects in interconnect structures Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required. Patterning, cleaning, and filling at nano dimensions Integration of new processes and structures, including interconnects for emerging devices Identify solutions which address global wiring scaling issues* >45 nm <45 nm Difficult Challenges * Top three grand challenges

8. Engineering manufacturable structures • Combinations and interactions of new materials and technologies • interfaces, contamination, adhesion, diffusion, leakage concerns, CMP damage, resist poisoning, thermal budget, ESH, CoO • Structural complexity • levels - interconnect, ground planes, decoupling caps • passive elements • mechanical integrity • other SOC interconnect design needs (RF) • cycle time

9. Materials Challenges • Long term – size effects • Microstructural and atom scale effects • Continued introduction of materials • barriers/nucleation layers for alternate conductors - optical, low temp, RF, air gap • alternate conductors, cooled conductors • More reliability challenges

10. Reliability Challenges • Short term • New failure mechanisms with Cu/low k present significant challenges before volume production • Electrical, thermal and mechanical exposure • interface diffusion • interface delamination • Higher intrinsic and interface leakage in low k • Need for new failure detection methodology to establish predictive models

11. Attaining Dimensional Control • 3D CD of features • Multiple levels • performance and reliability implications • reduced feature size, new materials and pattern dependent processes • Process problems • Line edge roughness, trench depth and profile, via shape, etch bias, thinning due to cleaning, CMP effects. • Process interactions • CMP and deposition - dishing/erosion - thinning • Deposition and etch - to pattern multi-layer dielectrics • Patterning, cleaning and filling at nano dimensions • particularly DRAM contacts and dual damascene

12. Technology Requirements • Wiring levels including “optional levels” • Reliability metrics • Minimum wiring/via pitches by level • Performance metric • Planarization requirements • Conductor resistivity • Barrier thickness • Dielectric metrics including effective k

13. MPU HP Near Term Years Number of metal levels increases slightly New RC delay metric for a 1 mm line (level dependent) – increasing due to relaxation on dielectric constant

15. MPU HP Near Term Years Bulk and effective dielectric constants described Effective k relaxed from 2002 Cu at all nodes - conformal barriers – resistivity 2.2 mW-cm

16. Cu resistivity increase 5 p=0 Measured Cu resistivity without barrier material 4 3 Resistivity(μΩcm) 2 p=0.5 1 0 0 0.1 0.2 0.3 0.4 0.5 Line width (nm) Wire width < mean free path of electrons ↓ Surface scattering dominant p=0 (complete diffuse scattering) p=1 (specular scattering) ↓ Resistivity increases even if the barrier metal Is 0 thickness ↓ barrier/Cu interface smoothing might be a solution p: fraction of electrons having elastic collisions at wire surfaces

17. MPU HP Long Term Years Conductor effective resistivity (red) because of scattering effects - research required Atomic dimension barriers – zero thickness barrier desirable but not required

18. Small changes in A/R, specific via and contact resistance Contact A/R rises to >20 in 2018 - a red challenge - associated with 16 nm DRAM half pitch Low k in 2003 - Cu delayed to 2007 Identified need to distinguish embedded, flash, and traditional DRAM DRAM

19. Surface preparation • Cross TWG work from FEP • Technology requirements address: • Killer defect density and size • Back surface particles • Metallic and organic contamination • Dielectric constant change (increase) due to stripping, cleaning and rework

20. Global interconnect roadmap

21. Last words • Continued changes in materials • Develop solutions for emerging devices • Must manage 3D CD • System level solutions must be accelerated to address the global wiring grand challenge • Cu resistivity increase impact appears ~2006 • materials solutions alone cannot deliver performance - end of traditional scaling • integrated approach with design and packaging